DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species A and Group II, Species C, FIG. 14-15 in the reply filed on July 11, 2026 is acknowledged.
Applicant states claims 1-4 and 7-13 read upon the elected species.
Claims 5 and 6 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 11, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 15, 2024 and January 21, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement filed December 17, 2025 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 7-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1. The term “substantially greater” in claim 1 is a relative term which renders the claim indefinite. The term “substantially greater” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Claim 1 recites the limitation “wherein a first width of the first recess is substantially greater than a second width of the second recess” in the last paragraph of the claim language.
Regarding claim 9. Claim 9 recites the limitation "during the removal of the first portion and the second portion of the conductive material" in the first two lines of the claim language. There is insufficient antecedent basis for these limitation in the claim.
Claims 2-4, 7-13 are rejected due to their dependency on a 112(b) rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 13 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Wu (U.S. 2017/0069632).
Regarding claim 1. Wu discloses a method of manufacturing a memory device (FIG. 1A), comprising:
providing a semiconductor substrate (FIG. 1A, item 110) defined with a peripheral region (FIG. 1A, item 140) and an array region (FIG. 1A, item 124) at least partially surrounded by the peripheral region (FIG. 1A, item 140);
forming a first recess ([0038], i.e. the gate structures 130 are formed by forming trenches in the substrate 110) extending into the semiconductor substrate (FIG. 1A, item 110) and disposed in the array region (FIG. 1A, item 124); and
forming a word line (FIG. 1A, item 130) disposed within the first recess ([0038]),
wherein the formation of the word line (FIG. 1A, item 130) includes disposing an insulating layer (FIG. 1A, item 136) conformal to the first recess ([0038]), and forming a conductive member (FIG. 1A, item 132) having a second recess (FIG. 1A, item 160; [0038], i.e. The unfilled portions of the trenches are over the gate structures 130, and are referred to as recesses 160 hereafter) extending into the conductive member (FIG. 1A, item 132) and toward the semiconductor substrate (FIG. 1A, item 110),
wherein a first width (annotated FIG. 1A, item W1) of the first recess ([0038]) is substantially greater (annotated FIG. 1A, show W1 is substantially greater than W2) than a second width (Annotated FIG. 1A, item W2) of the second recess. (Annotated FIG. 1A, item 160)
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Regarding claim 2. Wu discloses all the limitations of the method according to claim 1 above.
Wu further discloses wherein the conductive member (FIG. 1A, item 132) is surrounded by the insulating layer (FIG. 1A, item 136).
Regarding claim 13. Wu discloses all the limitations of the method according to claim 1 above.
Wu further discloses wherein the conductive member includes titanium nitride (TiN) ([0036]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 4, 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over (U.S. 2017/0069632) as applied to claim 2 above, and further in view of Huang (U.S. 2021/0242211).
Regarding claim 3. Wu discloses all the limitations of the method according to claim 2 above.
Wu further discloses wherein the formation of the conductive member (FIG. 1A, item 132) includes disposing a conductive material ([0036]) covering the insulating layer (FIG. 1A, item 136) and the semiconductor substrate (FIG. 1A, item 110).
Wu fails to explicitly disclose removing the conductive material disposed over the semiconductor substrate and surrounded by the insulating layer to form the conductive member.
However Huang teaches removing (FIG. 11-12; [0056], i.e. The formation of the word lines 144 includes (1) performing one or more removal processes, including a polishing process and/or an etching process, to remove the overlying layer 230 and portions of the insulative material 150, the conductive material 140, the diffusion barrier layer 140 and the dielectric film 130 above the underlying layer 220) the conductive material (FIG. 10-11, item 140) disposed over the semiconductor substrate (FIG. 10-11, item 110) and surrounded ([0054], i.e. conductive material 140 is conformally and uniformly deposited over the dielectric film 120) by the insulating layer (FIG. 10-11, item 120) to form the conductive member (FIG. 11, item 142).
Since both Wu and Huang teach Memory Devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of manufacturing a memory device as disclosed in Wu with the removing the conductive material disposed over the semiconductor substrate and surrounded by the insulating layer to form the conductive member as disclosed by Huang. The use of performing one or more removal processes, including a polishing process and/or an etching process, to remove the overlying layer and portions of the insulative material, the conductive material, the diffusion barrier layer and the dielectric film above the underlying layer in Huang provides for formation on the word lines (Huang, [0056]).
Regarding claim 4. Wu and Huang discloses all the limitations of the method according to claim 3 above.
Huang et al further discloses wherein the removal of the conductive material includes removing a first portion of the conductive material disposed over the semiconductor substrate ([0056], i.e. After the one or more removal processes, the underlying layer 220 is exposed, and a remaining dielectric film 122, a remaining diffusion barrier layer 132, a remaining conductive layer 142, and a plurality of insulative pieces 152 are formed), and removing a second portion of the conductive material surrounded by the insulating layer (FIG. 11-12; [0056], i.e. The formation of the word lines 144 includes (1) performing one or more removal processes, including a polishing process and/or an etching process, to remove the overlying layer 230 and portions of the insulative material 150, the conductive material 140, the diffusion barrier layer 140 and the dielectric film 130 above the underlying layer 220).
Regarding claim 7. Wu and Huang discloses all the limitations of the method according to claim 3 above.
Wu discloses further comprising disposing a dielectric material over (FIG. 1A, item 152) the semiconductor substrate (FIG. 1A, item 110) and the insulating layer (FIG. 1A, item 136), the conductive material (FIG. 1A, item 132) is on the insulating layer (FIG. 1A, item 136).
Huang discloses wherein the conductive material (FIG. 10, item 140) is disposed ([0051]-[0056]) on the dielectric material (FIG. 10, item 150) and the insulating layer (FIG. 10, item 130
Regarding claim 8. Wu and Huang discloses all the limitations of the method according to claim 7 above.
Huang further discloses wherein the dielectric material (FIG. 10, item 150) is disposed after the disposing of the insulating layer (FIG. 9-10, item 120)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jen et al (U.S. 10,083,906) Memory Device With Buried Word Line For Reduced Gate-induced Drain Leakage Current And Method For Manufacturing The Same.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.B./ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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