Prosecution Insights
Last updated: October 02, 2026
Application No. 18/638,088

SEMICONDUCTOR ELECTRODE STRUCTURES AND METHODS OF FORMING SAME

Non-Final OA §103
Filed
Apr 17, 2024
Examiner
ANDREWS, FELIX BRYAN
Art Unit
2881
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
50 granted / 62 resolved
+12.6% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
24 currently pending
Career history
81
Total Applications
across all art units

Statute-Specific Performance

§103
75.0%
+35.0% vs TC avg
§102
20.6%
-19.4% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 62 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-2 & 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Bristol et al (US 2023/0369206) & Ray et al. (US 2024/0213139). Regarding claim 1, Bristol teaches A method of forming an electrode structure for an electron beam steering device, the method comprising: disposing a first hard mask layer [fig. 3, layer 304, para 57] ; forming a first cavity and a second cavity in the first hard mask layer [annotated fig. 3(iii)], the first cavity passing through the first hard mask layer (fig. 3, 304), and the second cavity passing through the first hard mask layer (fig. 3, 304); filling the first cavity and the second cavity with an electrically conductive material to form a first electrically conductive pillar and a second electrically conductive pillar [fig. 3, conductive structure 308, para 59]; performing a first planarization process on an exposed surface of the first electrically conductive pillar and an exposed surface of the second electrically conductive pillar [para 59]; after performing the first planarization process, disposing a second hard mask layer [fig. 3(v), layer 312, para 61] on the first hard mask layer (fig. 3(v), 304), the second hard mask layer (fig. 3(v), 312) covering the planarized exposed surface of the first electrically conductive pillar and the planarized exposed surface of the second electrically conductive pillar (fig. 3(v)); forming a third cavity in the second hard mask layer passing through the second hard mask layer to the second electrically conductive pillar [fig. 3(vii)]; filling the third cavity with the electrically conductive material to form a third electrically conductive pillar [fig. 3(ix), conductive structure 316, para 64] contacting the second electrically conductive pillar [annotated fig. 3(ix)]; performing second planarization process on an exposed surface of the third electrically conductive pillar [para 64]; and removing the first hard mask layer and the second hard mask layer to expose the first, second and third electrically conductive pillars [fig. 3(ix); wherein the layer 304 and layer 312 have been removed to expose the pillars electrically connected to the top surface], wherein a first electrode comprises the first electrically conductive pillar [annotated fig. 3(ix)], and a second electrode comprises a combination of the second and third electrically conductive pillars [annotated fig. 3(ix)]. While Bristol further notes in para 38 in an exemplary embodiment that lower hard mask layer may be above an underlying metallization layer. Bristol fails to explicity disclose the first hard mask on a driver circuit including a patterned metallization layer. However, Ray teaches the first hard mask [fig. 2A, 102, para 31]on a driver circuit [fig. 2A, superstructure 110, para 30 including a patterned metallization layer [fig. 2A, metallization layers M1, para 30]. Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to utilize a hard mask on a driver circuit including a metallization layer to enable precise pattern transfer and maintain critical dimension during etching. PNG media_image1.png 580 801 media_image1.png Greyscale ANNOTATED FIG. 3(iii) PNG media_image2.png 998 1201 media_image2.png Greyscale ANNOTATED FIG. 3(ix) Regarding claim 2, Bristol/Ray teaches The method of claim 1, wherein the third cavity has a smaller cross-sectional width than the second cavity, and the third electrically conductive pillar has a smaller cross-sectional width than the second electrically conductive pillar [Bristol, fig. 3(ix) illustrates the third cavity and pillar are smaller in width than the second cavity and pillar]. Regarding claim 4, Bristol/Ray teaches The method of claim 1, wherein the driver circuit includes a transistor (Ray, fig. 1, 110; illustrates to FETs in the driver circuit) that is electrically connected with the first electrode by the patterned metallization layer of the driver circuit [Ray, fig. 1 illustrates the transistors connected to the first metallization layers. Fig. 2 further discloses M1 layer connected to the electrode 210]. Regarding claim 5, Bristol/Ray teaches The method of claim 1, wherein the first (Bristol, 304, para 56) and second hard mask (Bristol, 312, para 61) layers comprise silicon, a dielectric material (Bristol, para 56/61) and/or polymer; and the electrically conductive material is Cu, Ag, Al or a compound metal [Bristol, para 95, discloses copper as an exemplary conductive material. Therefore it would be obvious to one ordinary skill to utilize copper as a material for any conductive material]. Regarding claim 6, Bristol/Ray teaches The method of claim 1, wherein the steps of disposing a second hard mask layer (fig. 3, 312), patterning the second hard mask layer (fig. 3), filling the second hard mask third cavity with an electrically conductive material [fig. 3(ix), conductive structure 316, para 64], and performing a second planarization process [para 64] are repeatedly performed for a plurality of stacked second hard mask layers [fig. 3(vii-viii); wherein the process is performed on layer 314 and 312 to form the third conductive pillar] to form the third electrically conductive pillar (annotated fig. 3(ix)). Allowable Subject Matter Claims 9-16 & 21-24 are allowed. Claims 3 & 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 3, Bristol/Ray teaches The method of claim 1. The prior art of record fails to explicitly disclose in entirety wherein the driver circuit comprises a silicon substrate and the method further comprises: forming an electron beam pass-through comprising a through silicon via passing through the silicon substrate, wherein the first electrode comprises two first electrodes, the second electrode comprises two second electrodes, and the electron beam pass-through is disposed between the two first electrodes and between the two second electrodes. Thereby claim 3 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 7, Bristol/Ray teaches the method of claim 1. The prior art fails to explicitly disclose wherein a first cross-sectional width of the first electrically conductive pillar and the second electrically conductive pillar has a standard deviation of less than 0.2um; an angle between a lateral axis of an exposed end surface of the first electrode and a longitudinal axis of the first electrode is 85 to 95 degrees; and a second cross-sectional width of the third electrically conductive pillar has a standard deviation of less than 0.2um. Thereby claim 7 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 8, Bristol/Ray teaches The method of claim 1. The prior art of record fails to explicitly disclose wherein a first longitudinal length of the first electrically conductive pillar and the second electrically conductive pillar is 1-100um; a first cross-sectional width of the first electrically conductive pillar and the second electrically conductive pillar is 1-100um; a second longitudinal length of the third electrically conductive pillar is 1- 100um; the second cross-sectional width of the third electrically conductive pillar is 1- 100um; a minimum spacing of the first electrically conductive pillar and the second electrically conductive pillar is less than 5um; and an aspect ratio is 1-30, the aspect ratio defined as ( the first longitudinal length the second longitudinal length)/the first cross-sectional width. Thereby claim 8 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 9 the prior art of record fails to explicitly disclose in entirety A method of forming an electrode structure for an electron beam steering device, the method comprising: disposing a first hard mask layer on the driver circuit; forming an array of first cavities passing through the first hard mask layer and an array of second cavities passing through the first hard mask layer, wherein each of a plurality of the electron beam pass-throughs is between one of the first cavities and one of the second cavities; by electroplating, filling the first cavities with an electrically conductive material to form an array of first electrically conductive pillars and the second cavities to form an array of second electrically conductive pillars; planarizing exposed surfaces of the first and second electrically conductive pillars; disposing a second hard mask layer on the first hard mask layer and over the planarized exposed surfaces of the first and second electrically conductive pillars; forming an array of third cavities passing through the second hard mask layer wherein the array of third cavities is aligned with the array of second electrically conductive pillars; by electroplating, filling the third cavities with the electrically conductive material to extend a height of the second electrically conductive pillars; planarizing exposed surfaces of the extended-height second electrically conductive pillars; and removing the first hard mask layer and the second hard mask layer to expose an array of first electrodes consisting of the array of first electrically conductive pillars and an array of second electrodes consisting of the array of extended-height second electrically conductive pillars. Thereby claim 9 contains allowable subject matter. Claims 10-16 contain allowable subject matter at least based upon their dependency on claim 9. Regarding claim 21, the prior art fails to explicitly disclose in entirety A method of forming an e-beam steering device, the method comprising: forming a driver circuit including electron beam pass-throughs, driving transistors, and a patterned metallization layer; and forming first electrodes and second electrodes, wherein: the second electrodes have a higher height than the first electrodes, each electron beam pass-through has a first electrode a second electrode on opposite sides of the electron beam pass-through, and the second electrodes have a lower portion proximate to the driver circuit with a first cross-sectional width and an upper portion distal from the driver circuit with a second cross-sectional width that is smaller than the first cross-sectional width. Thereby claim 21 contains allowable subject matter. Claims 22 – 24 contain allowable subject matter at least based upon their dependency on claim 21. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FELIX B ANDREWS/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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Prosecution Timeline

Apr 17, 2024
Application Filed
Sep 11, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
86%
With Interview (+5.1%)
3y 3m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 62 resolved cases by this examiner. Grant probability derived from career allowance rate.

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