DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention III, Claims 13-20 in the reply filed on 08/03/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/03/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13 - 18 are rejected under U.S.C. 103 as being unpatentable over Shimatani et al.; US 12,745,563 B2; 01/2023 in view of Chung; US 2004/0142535 A1; 12/2003
Claim 13: Shimatani discloses a method of forming a semiconductor device, comprising: forming a lower electrode layer ( Fig. 2 electrode pair 2a and 2b ); depositing a first barrier layer ( Fig. 2 first insulating film ) on the lower electrode layer ( Fig. 2 #2a and #2b ); forming a dielectric layer ( Fig. 2 first ferroelectric layer 5 ) on the second barrier layer ( Col. 12 lines 35 – 40 A thickness of first insulating film 3 is not particularly limited as long as first electrode pair 2a and second electrode pair 2b are electrically insulated from first ferroelectric layer 5 ); and forming a top electrode layer on the dielectric layer ( Fig. 2 back electrode 4 ).
Shimatani does not appear to disclose depositing a second barrier layer on the first barrier; so that the first barrier layer and the second barrier layer form a barrier layer.
However, Chung teaches depositing a second barrier ( Fig. 8 barrier layer 370 ) layer on the first barrier ( Fig. 8 barrier layer 350 ); so that the first barrier layer and the second barrier layer form a barrier layer ( as shown in Fig. 8 )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chung with Shimatani to implement depositing a second barrier layer on the first barrier; so that the first barrier layer and the second barrier layer form a barrier layer because this approach optimizes interfacial stress.
Claim 14: Shimatani and Chung disclose the method of claim 13 ( as described above ).
Shimatani does not appear to disclose depositing the first barrier layer is performed after forming the lower electrode layer.
However, Chung teaches depositing the first barrier layer ( Fig. 8 #350 ) is performed after ( [0025] after forming a second barrier layer 350 and a third barrier layer 370 on the metal layer 300 ) forming the lower electrode layer ( Fig. 8 #300 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chung with Shimatani to implement depositing the first barrier layer is performed after forming the lower electrode layer because this approach prevents unwanted chemical reactions, diffusion, and oxidation at the interface between the metal electrode and the dielectric layer.
Claim 15: Shimatani and Chung disclose the method of claim 13 ( as described above ).
Shimatani does not appear to disclose depositing the second barrier layer is performed after depositing the first barrier layer.
However, Chung teaches depositing the second barrier layer is performed after depositing the first barrier layer ( [0025] after forming a second barrier layer 350 and a third barrier layer 370 on the metal layer 300 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chung with Shimatani to implement depositing the second barrier layer is performed after depositing the first barrier layer because this can be used to resolve conflicting material requirements so that one is an adhesion promoter while the second is a diffusion barrier.
Claim 16: Shimatani and Chung disclose the method of claim 13 ( as described above ),
Shimatani teaches depositing the first barrier layer is performed by an ozone treatment ( Col. 14 lines 9-11 A method for forming first insulating film 3 may be a chemical vapor deposition (CVD) method or a sputtering method; where CVD involves the use of ozone ).
Claim 17: Shimatani and Chung disclose the method of claim 13 ( as described above ).
Shimatani teaches a process temperature of depositing the first barrier layer is in a range between 200 Celsius degrees (*C) and 400 Celsius degrees (*C) ( Col. 14 lines 9-11 A method for forming first insulating film 3 may be a chemical vapor deposition (CVD) method or a sputtering method; the process temperature for CVD generally ranges from 200 degrees C to 1150 degrees C ).
Claim 18: Shimatani and Chung disclose the method of claim 13 ( as discussed above ).
Shimatani teaches depositing the first barrier layer is performed by using ozone ( Col. 14 lines 9-11 A method for forming first insulating film 3 may be a chemical vapor deposition (CVD) method or a sputtering method; where CVD involves the use of ozone ), and the ozone has a density in a range between 50 grams per cubic meter (g/m3) and 500 grams per cubic meter (g/ma) ( Specification sheets for CVD machines verify ozone concentrations in these ranges ).
Claims 19 - 20 are rejected under U.S.C. 103 as being unpatentable over Shimatani et al.; US 12,745,563 B2; 01/2023 in view of Chung; US 2004/0142535 A1; 12/2003 as it relates to claim 13 above and further in view of Mutyala et al.; US 2025/0226203 A1; 01/2024
Claim 19: Shimatani and Chung disclose the method of claim 13 ( as discussed above).
Neither Shimatani nor Chung appear to disclose depositing the second barrier layer is performed by using nitrogen plasma.
However, Mutyala teaches depositing the second barrier layer is performed by using nitrogen plasma ( [0040] The first barrier layer 404, conductive layer 406, and/or second barrier layer 408 may be deposited and/or doped by any appropriate deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or the like; where nitrogen plasma is part of the PECVD process ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Mutyala with Shimatani and Chung to implement depositing the second barrier layer is performed by using nitrogen plasma because this technique is utilized in the PECVD process.
Claim 20: Shimatani and Chung disclose the method of claim 13 ( as discussed above).
Neither Shimatani nor Chung appear to disclose a process temperature of depositing the second barrier layer is in a range between 200 Celsius degrees (*C) and 600 Celsius degrees (0C).
However, Mutyala teaches a process temperature of depositing the second barrier layer is in a range between 200 Celsius degrees (*C) and 600 Celsius degrees (0C) ( PECVD process temperature ranges from 200 to 400 degrees Celsius).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Mutyala with Shimatani and Chung to implement a process temperature of depositing the second barrier layer is in a range between 200 Celsius degrees (*C) and 600 Celsius degrees (0C) because this is the process temperature range of PECVD.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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