Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the application filed on 04/18/2024. Currently, claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, 11, 15 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 20210013138 A1).
Regarding claim 1, Figure 2A of Kim discloses a semiconductor package structure, comprising:
a carrier (12/120/122, [0018]);
a first chip (180, [0018]), disposed on the carrier;
a second chip (150, [0017]), disposed on the first chip;
a plurality of bonding wires (136, [0018]), arranged to electrically connect the first chip (180) and the carrier (120); and
a plurality of first bumps (153, [0016]), arranged to electrically connect the second chip and the first chip, wherein the plurality of first bumps is sandwiched between the second chip (150) and the first chip (180).
Regarding claim 2, Figure 2A of Kim discloses that the semiconductor package structure of claim 1, wherein at least one of the first bumps (153) is arranged to be an Input/Output ([0006]) connection path between the first chip (180) and the second chip (150).
Regarding claim 3, Figure 2A of Kim discloses that the semiconductor package structure of claim 1, wherein the first chip (180) is disposed on the carrier (12/120/122) in a manner that a back surface (at 177) of the first chip faces the carrier.
Regarding claim 4, Figure 2A of Kim discloses that the semiconductor package structure of claim 1, wherein the second chip (150) is disposed on the first chip (180) in a manner that a front surface (at 151) of the second chip faces a front surface (at 188) of the first chip.
Regarding claim 5, Figure 2A of Kim discloses that the semiconductor package structure of claim 4, wherein, for each of the first bumps (153), one end of the first bump is attached to a first pad (188) formed on the front surface of the first chip, and the other end of the first bump is attached to a second pad (151) formed on the front surface of the second chip.
Regarding claim 7, Figure 2A of Kim discloses that the semiconductor package structure of claim 4, wherein, for each of the bonding wires (136), one end of the bonding wire is connected to a first pad (181) formed on the front surface of the first chip, and the other end of bonding wire is electrically connected to the carrier (12/120/122).
Regarding claim 11, Figure 2A of Kim discloses that the semiconductor package structure of claim 1, wherein the first bump comprises a micro-bump, a hybrid-bump or a nano-bump (considering a micro-bump on a broadest reasonable interpretation since no limit is put in the claim).
Regarding claim 15, Figure 2A of Kim discloses that the semiconductor package structure of claim 1, wherein the carrier (12/120/122) comprises a lead frame ([0018]).
Regarding claim 19, Figure 2A of Kim discloses that the semiconductor package structure of claim 1, further comprising an adhesive layer (177) disposed between a back surface of the first chip and the carrier, and a material of the adhesive layer comprises Ajinomoto build-up film (ABF), polyimide resin or epoxy resin ([0018]).
Regarding claim 20, Figure 2A of Kim discloses that the semiconductor package structure of claim 1, further comprising an encapsulation layer (190) at least encapsulating the carrier, the first chip (180), the plurality of bonding wires (136), the second chip and the plurality of first bumps, and a material of the encapsulation layer comprises a molding compound ([0014]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 12-14 and 18 are rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 20210013138 A1).
Regarding claims 6, 12-14 and 18, Figure 2A of Kim does not teach that the semiconductor package structure of claim 5, wherein thicknesses of the first pad, the first bump, and the second pad substantially cause a distance between the first chip and the second chip, and the distance is ranged about 50˜150 μm. Or
The semiconductor package structure of claim 1 wherein a pitch between the first chip and the second chip is less than 1 mm. Or
The semiconductor package structure of claim 1, wherein the pitch between the first chip and the second chip is less than 150 μm. Or
The semiconductor package structure of claim 1, wherein a size of the second chip is 16 mm.sup.2 or less. Or
The semiconductor package structure of claim 1, wherein the plurality of first bumps comprises at least 100 first bumps.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges for an improved device with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 8-10 are rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 20210013138 A1) in view of Payne et al (US 6057598 A).
Regarding claims 8-10, Figure 2A of Kim does not explicitly teach that the semiconductor package structure of claim 1, wherein the first chip comprises a system-on-chip (SoC) with an advanced RISC machine (ARM) architecture. Or
The semiconductor package structure of claim 1, wherein the second chip comprises a memory chip, wherein the memory chip comprises a dynamic random access memory (DRAM)-based chip with a one-transistor-one-capacitor (1T1C) architecture.
However, Payne is a pertinent art which a logic circuit die with a memory circuit die in a single integrated circuit device capable of supporting memory intensive applications, such as 3-dimensional graphics rendering, encryption and signal processing. The logic circuit die is produced independently with a logic circuit fabrication process that optimizes the logic circuit's performance and reduces costs, and the memory circuit die, which may contain a large memory circuit, can be produced independently with a memory circuit fabrication process that optimizes the memory circuit's performance and reduces costs. The circuit dies are attached directly together in a flip-chip fashion to create a unitary integrated circuit assembly (Figure 4) having a high-performance, low impedance, wide-word interface. This integrated circuit assembly can be enclosed within a typical integrated circuit package for insertion on a circuit board, such as those used in personal computers and other common electronic applications (Abstract and Background) (Col. 6 and lines 58-3), wherein random access memory (DRAM)-based chip with a one-transistor-one-capacitor (1T1C) architecture very well known in prior arts.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Kim , wherein the first chip comprises a system-on-chip (SoC) with an advanced RISC machine (ARM) architecture or wherein the second chip comprises a memory chip, wherein the memory chip comprises a dynamic random access memory (DRAM)-based chip with a one-transistor-one-capacitor (1T1C) architecture according to the teaching of Payne in order to form a package with high performance and low cost (Abstract of Payne).
Claims 16-17 are rejected under 35 U.S.C. 103 as being obvious over Kim et al (US 20210013138 A1) in view of Kwon et al (US 20050242426 A1).
Regarding claims 16-17, Figure 2A of Kim does not explicitly teach that the semiconductor package structure of claim 1, wherein the carrier comprises a printed circuit board (PCB) or a circuit substrate comprising a printed circuit board and an interposer disposed on and electrically connected to the printed circuit board and further comprising a plurality of second bumps disposed on a surface of the carrier opposite to the first chip.
However, Kwon is a pertinent art which teaches a semiconductor package comprises a base frame and a lower semiconductor chip electrically coupled to the base frame. The lower semiconductor chip has a first bond pad formed on a top surface thereof. The package further includes an upper semiconductor chip overlying the lower semiconductor chip. The upper semiconductor chip has a third bond pad formed on a bottom surface thereof. The package comprises a first conductive bump and a second conductive bump jointly coupling the first bond pad to the third bond pad. Kwon, further, teaches a flexible printed circuit board (PCB) or a rigid type PCB may be used as the base frame 110. A base frame generally employed for a ball grid array (BGA) may be used as the base frame 110. Then, the lower semiconductor chip 120 is mounted on the base frame 110, preferably, using the adhesive 160 such as an adhesive tape or epoxy. The first bond pad 122 suitable for flip chip bonding is formed on the central portion of the lower semiconductor chip 120, and the second bond pad 132 for wire bonding is formed on the edge portion of the lower semiconductor chip 120. The gold bump 124 is formed on the first bond pad 122. The lower semiconductor chip 120 may act as a microprocessor, an LSI, or a logic device ([0049]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Kim by using printed circuit board as a carrier, wherein the carrier comprises a printed circuit board (PCB) or a circuit substrate comprising a printed circuit board and an interposer disposed on and electrically connected to the printed circuit board and further comprising a plurality of second bumps disposed on a surface of the carrier opposite to the first chip according to the teaching of Kwon in order to form a semiconductor package for a microprocessor, an LSI, or a logic device with smaller size ([0006] of Kwon).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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