Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, with traverse, of claims 1-17 in the reply filed on June 30th, 2026, is acknowledged. The traversal is on the ground(s) that “the USPTO has not met its burden in supporting the restriction requirement”. This is not found persuasive. The restriction for examination purposes as indicated in the restriction /election requirement, mailed on 05/13/2026, is proper because all these inventions listed in this action are independent or distinct for the reasons given and there would be a serious search and examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classification;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries);
(d) the prior art applicable to one invention would not likely be applicable to another invention;
(e) the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Accordingly, the requirement is still deemed proper and is therefore made FINAL.
Non-elected invention and species, claims 18-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Group I, claims 1-17 as follows.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 18th, 2024 has been considered by the examiner.
Drawings
The drawings filed on 04/18/2024 are objected.
Figures 1A and 1B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features: “an insulating sheath disposed around each of the set of conductive bars to mechanically connect the set of conductive bars together but electrically isolate the set of conductive bars from each other”, as recited in dependent claim 8, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-7, 9-10, 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Buot (US 2022/0238488, hereinafter as Buot ‘488) in view of Ganesan (US 2021/0028116, hereinafter as Gane ‘116).
Regarding Claim 1, Buot ‘488 teaches a semiconductor device, comprising:
a substrate (Fig. 1, (170); [0026]) having a set of conductive patterns (172; [0026]);
a semiconductor die (110/120; [0025]) mounted on the substrate, wherein the semiconductor die has on its top surface a set of bonding pads (Fig. 1, (BP_Annotated)); and
a conductive bar assembly (160; [0027]) for electrically connecting the set of conductive patterns (172) of the substrate with the set of bonding pads (BP) of the semiconductor die, wherein the set of conductive bars to be electrically connected to the set of conductive patterns of the substrate and a set of second ends to be electrically connected to the set of bonding pads of the semiconductor die.
Thus, Buot ‘488 is shown to teach all the features of the claim with the exception of explicitly the limitations: “the conductive bar assembly comprises: an insulating body; and a set of conductive bars extending within the insulating body, wherein the set of conductive bars have a set of first ends exposed from a first surface of the insulating body and a set of second ends exposed from a second surface of the insulating”.
Gane ‘116 teaches the conductive bar assembly (Fig. 2D, (230); [0041]) comprises: an insulating body (dielectric layers, see para. [0030]); and a set of conductive bars (164; [0030]) extending within the insulating body, wherein the set of conductive bars (164) have a set of first ends exposed from a first surface of the insulating body and a set of second ends exposed from a second surface of the insulating body (see Fig. 2D).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Buot ‘488 by having the conductive bar assembly for the purpose of optimizing for low loss transmission of high speed, high bandwidth I/O signaling.(see para. [0025]) as suggested by Gane ‘116.
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Fig. 1 (Sir ‘488_Annotated)
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Fig. 2D (Gane ‘116)
Regarding Claim 2, Buot ‘488 teaches the second ends of the conductive bars (160) are aligned with the set of bonding pads (BP_Annotated) of the semiconductor die (120) in a vertical direction of the substrate.
Regarding Claim 3, Gane ‘116 teaches the conductive bar assembly (230) is a preformed piece (see Fig. 2D).
Regarding Claim 4, Gane ‘116 teaches the insulating body comprises a base and a cover, and the set of conductive bars (264) are disposed between the base and the cover (see Fig. 2D).
Regarding Claim 5, Gane ‘116 teaches the first surface is a bottom surface of the insulating body, and the second surface is a lateral surface of the insulating body (see Fig. 2F).
Regarding Claim 6, Gane ‘116 teaches the first surface is a bottom surface of the insulating body, and the second surface is a top surface of the insulating body (see Fig. 2D).
Regarding Claim 7, Gane ‘116 teaches the second surface is a second lateral surface of the insulating body (see Fig. 2F).
Thus, Buot ‘488 and Gane ‘116 are shown to teach all the features of the claim with the exception of explicitly the limitations: “first surface is a first lateral surface of the insulating body”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have first surface that can be arranged in any order, thus the first surface is a first lateral surface of the insulating body involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to have the first surface is a first lateral surface of the insulating body when this improves the connectivity of the package semiconductor device.
Regarding Claim 9, Buot ‘488 teaches the semiconductor die is a first semiconductor die (120), and the semiconductor device further comprises: a second semiconductor die (110; [0025]) mounted between the substrate (170) and the first semiconductor die (120), wherein the second semiconductor die (110) is attached onto another set of conductive patterns on the substrate, and the first semiconductor die is attached to the second semiconductor die via adhesive (130; [0025]).
Regarding Claim 10, Buot ‘488 teaches the second semiconductor die (110; [0025]) is a flip chip type semiconductor die.
Regarding Claim 12, Buot ‘488 teaches the semiconductor device is a unit type semiconductor device (see Fig. 1).
Regarding Claim 17, Gane ‘116 teaches the first surface and the second surface are a same surface of the insulating body (see Fig. 1A).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Buot ‘488 and Gane ‘116 as applied to claim 1 above, and further in view of Ito (US 2019/0279790, hereinafter as Ito ‘790).
Regarding Claim 8, Buot ‘488 and Gane ‘116 are shown to teach all the features of the claim with the exception of explicitly the limitations: “an insulating sheath disposed around each of the set of conductive bars to mechanically connect the set of conductive bars together but electrically isolate the set of conductive bars from each other”.
Ito ‘790 teaches an insulating sheath (Fig. 2B, (13); [0040]) disposed around each of the set of conductive bars (12; [0040]) to mechanically connect the set of conductive bars together but electrically isolate the set of conductive bars from each other (see Fig. 2B).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Buot ‘488 and Gane ‘116 by having an insulating sheath disposed around each of the set of conductive bars to mechanically connect the set of conductive bars together but electrically isolate the set of conductive bars from each other in order to improve the workability of processing and contribute to facilitated manufacturing (see para. [0018]) as suggested by Ito ‘790.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Buot ‘488 and Gane ‘116 as applied to claim 1 above, and further in view of Choi (US 2015/0001703, hereinafter as Choi ‘703).
Regarding Claim 8, Buot ‘488 and Gane ‘116 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the semiconductor device is a strip type semiconductor device”.
Choi ‘703 teaches the semiconductor device is a strip type semiconductor device (see para. [0038]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Buot ‘488 and Gane ‘116 by having the semiconductor device is a strip type semiconductor device in order to provide a plurality of semiconductor die (see para. [0011]) as suggested by Choi ‘703.
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Buot ‘488 and Gane ‘116 as applied to claim 1 above, and further in view of Embong (US 2002/0066963, hereinafter as Embo ‘963).
Regarding Claim 13, Gane ‘116 teaches the conductive bar assembly (Fig. 2D, (230); [0041]) comprises: an insulating body (dielectric layers, see para. [0030]); and a set of conductive bars (164; [0030]) extending within the insulating body, wherein the set of conductive bars (164) have a set of first ends exposed from a first surface of the insulating body and a set of second ends exposed from a second surface of the insulating body (see Fig. 2D).
Buot ‘488 and Gane ‘116 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a second set of conductive patterns and the semiconductor die has on its top surface a second set of bonding pads; and wherein the semiconductor device further comprises: a second conductive bar assembly for electrically connecting the second set of conductive patterns of the substrate with the second set of bonding pads of the semiconductor die, wherein the set of conductive bars have a set of first ends to be electrically connected to the second set of conductive patterns of the substrate and a set of second ends to be electrically connected to the second set of bonding pads of the semiconductor die”.
Embo ‘963 teaches a second set of conductive patterns (Fig. 13, (1122); [0044]) and the semiconductor die has on its top surface a second set of bonding pads; and wherein the semiconductor device further comprises: a second conductive bar assembly (1232) for electrically connecting the second set of conductive patterns of the substrate with the second set of bonding pads of the semiconductor die, wherein the set of conductive bars have a set of first ends to be electrically connected to the second set of conductive patterns of the substrate and a set of second ends to be electrically connected to the second set of bonding pads of the semiconductor die (see Fig. 13).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Buot ‘488 and Gane ‘116 by having a second set of conductive patterns and the semiconductor die has on its top surface a second set of bonding pads; and wherein the semiconductor device further comprises: a second conductive bar assembly for electrically connecting the second set of conductive patterns of the substrate with the second set of bonding pads of the semiconductor die, wherein the set of conductive bars have a set of first ends to be electrically connected to the second set of conductive patterns of the substrate and a set of second ends to be electrically connected to the second set of bonding pads of the semiconductor die in order to improve semiconductor component (see para. [0048]) as suggested by Embo ‘963.
Regarding Claim 14, Embo ‘963 teaches the conductive bar assembly and the second conductive bar assembly are disposed at two different sides of the semiconductor die (1120; [0044]) (see Fig. 13).
Regarding Claim 15, Buot ‘488, Gane ‘116 and Embo ‘963 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the conductive bar assembly and the second conductive bar assembly are disposed at a same side of the semiconductor die”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second conductive bar assembly that can be arranged in any order, thus the conductive bar assembly and the second conductive bar assembly are disposed at a same side of the semiconductor die involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to have the conductive bar assembly and the second conductive bar assembly are disposed at a same side of the semiconductor die when this improves the performance of the package semiconductor device.
Regarding Claim 16, Buot ‘488, Gane ‘116 and Embo ‘963 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the conductive bar assembly and the second conductive bar assembly at least partially overlap with each other”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second conductive bar assembly that can be arranged in any order, thus the conductive bar assembly and the second conductive bar assembly at least partially overlap with each other involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to have the conductive bar assembly and the second conductive bar assembly at least partially overlap with each other when this improves the performance of the package semiconductor device.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraph numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Suthiwongsunthorn et al. (US 2015/0102478 A1)
Lee et al. (US 2014/0191380 A1)
Awujoola et al. (US 2005/0104164 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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