Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 14-17, the preamble of “The semiconductor structure as claimed..” is incorrect due to the claims being dependent to a method of manufacturing claim (claim 13). It is suggested for the applicant to fix this error.
Claims 14-17 will still be examined below as a method dependent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10-12, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US-20220367670-A1 referred as Lai) in view of Jain et al. (US-20250120175-A1 referred as Jain) and Chen et al. (CN-114975249-A referred as Chen).
Regarding claim 1. Lai discloses a semiconductor structure, comprising:
a first well region and a second well region displaced from each other, a conductivity type of the first well region being opposite to a conductivity type of the second well region ([0013], figure 16, the substrate #202 includes a p-type first well region #1000 and a n-type second well region #2000);
a first semiconductor device formed on the first well region and including a first channel ([0014], figure 16, a first semiconductor device #260 formed on the first well region #1000 and including a first channel #208),
two first source/drain portions which are respectively located at two opposite sides of the first channel, a conductivity type of the two first source/drain portions being opposite to the conductivity type of the first well region ([0026], figure 16, two first source/drain portions #232 are located at two opposite sides of the first channel #208, furthermore the conductivity type of the two first source/drain portions #232 includes n-type dopants (which is opposite of the conductivity type seen in the first well region #1000)); and
a second semiconductor device formed on the second well region and including a second channel ([0014], figure 16, a second semiconductor device #280 formed on the second well region #2000 and including a second channel #208),
two second source/drain portions which are respectively located at two opposite sides of the second channel, a conductivity type of the two second source/drain portions being opposite to the conductivity type of the second well region ([0031], figure 16, two second source/drain portions #238 are located at two opposite sides of the second channel #208, furthermore the conductivity type of the two second source/drain portions #238 includes p-type dopants (which is opposite of the conductivity type seen in the second well region #2000)).
Lai lacks at least one first isolation feature including a first doped semiconductor portion and a first insulating portion which are respectively in contact with the first well region and a corresponding one of the two first source/drain portions, a conductivity type of the first doped semiconductor portion being the same as the conductivity type of the two first source/drain portions; and
at least one second isolation feature including a second insulating portion disposed to separate the second well region from a corresponding one of the two second source/drain portions.
Jain discloses at least one first isolation feature including a first insulating portion which are respectively in contact with a corresponding one of the two first source/drain portions ([0022], figure 1, one isolation feature #102 (specifically in section #161) includes a first insulating portion #102 which is contact with one of the two first source/drain portions #106); and
at least one second isolation feature including a second insulating portion disposed to separate the second well region from a corresponding one of the two second source/drain portions ([0022], figure 1, one second isolation feature #102 (specifically in section #152) includes a second insulating portion #102 disposed to separate the second well region #113 from a corresponding one of the two second source/drain portions #106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai to include a first and second isolation feature in the semiconductor devices as taught by Jain in order to enhance electrical insulation, improve efficiency in the source/drain portion, and to increase the devices lifetime.
Lai as modified by Jain still lacks at least one first isolation feature including a first doped semiconductor portion which is respectively in contact with the first well region, a conductivity type of the first doped semiconductor portion being the same as the conductivity type of the two first source/drain portions.
Chen discloses at least one first isolation feature including a first doped semiconductor portion which is respectively in contact with the first well region, a conductivity type of the first doped semiconductor portion being the same as the conductivity type of the two first source/drain portions ([Pg 10 lines 3-11 in machine translation], figure 7a, one first isolation feature #56 includes a first doped semiconductor portion #56. In a embodiment, the first doped semiconductor portion #56 and the two first source/drain portions #60 have the same conductivity type of N-Type).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified by Jain to include at least one first isolation feature including a first doped semiconductor portion as taught by Chen in order to increase device versatility, enhance the devices efficiency, and to promote the process integration.
Regarding claim 2 and claim 3. Lai as modified lacks
[claim 2] wherein a dopant concentration of the first doped semiconductor portion is less than a dopant concentration of each of the two first source/drain portions by at least two to four orders of magnitude.
[claim 3] wherein a difference between a dopant concentration of the first doped semiconductor portion and a dopant concentration of the first well region is not greater than two orders of magnitude.
Chen discloses
[claim 2] wherein a dopant concentration of the first doped semiconductor portion is less than a dopant concentration of each of the two first source/drain portions by at least two to four orders of magnitude ([pg 10, lines 26-30 from the Machine Translation], figure 7a, the dopant concentration of the first doped semiconductor portion #56 is less than the dopant concentration of the first source/drain portion #60 by two orders of magnitude (as described exactly)).
[claim 3] wherein a difference between a dopant concentration of the first doped semiconductor portion and a dopant concentration of the first well region is not greater than two orders of magnitude ([pg 10, lines 26-30 from the Machine Translation], figure 7a, the dopant concentration of the first doped semiconductor portion #56 and the dopant concentration of the first well region #22 is within the range of two orders of magnitude (as described exactly)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified to include wherein a difference between a dopant concentration of the first doped semiconductor portion and a dopant concentration of the first well region and the first well region is at two orders of magnitude as taught by Chen in order to enhance carrier mobility, reduce defect formation and for better process control.
Regarding claim 10. Lai discloses a method for manufacturing a semiconductor structure, comprising:
forming a well region having a first conductivity type ([0013], figure 6, forming a well region #2000 at substrate #202 with a first conductivity type of n-type dopants);
forming a channel ([0014], figure 6, forming a channel #208);
forming two source/drain portions on the well region so that the two source/drain portions are respectively located at two opposite sides of the channel, the two source/drain portions having a second conductivity type which is opposite to the first conductivity type ([0031], figure 16, forming two source/drain portions #238 on the well region #2000 so that the source/drain portions #238 are at opposite ends of the chanel #208. Also the source/drain portions #238 have a second conductivity type of p-type dopants).
Lai lacks forming at least one isolation feature including a doped semiconductor portion and an insulating portion which are respectively in contact with the well region and a corresponding one of the two source/drain portions, the doped semiconductor portion having the second conductivity type.
Jain discloses forming at least one isolation feature including an insulating portion which is respectively in contact with a corresponding one of the two source/drain portions ([0022], figure 1, one isolation feature #105/102 (specifically in section #152) includes an insulating portion #102 a corresponding one of the two source/drain portions #106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai to include forming at least one isolation feature including a doped semiconductor portion and an insulating portion as taught by Jain in order to enhance electrical insulation, improve efficiency in the source/drain portion, and to increase the devices lifetime.
Lai as modified by Jain still lacks forming at least one isolation feature including a doped semiconductor portion which is respectively in contact with the well region, the doped semiconductor portion having the second conductivity type.
Chen discloses forming at least one isolation feature including a doped semiconductor portion which is respectively in contact with the well region, the doped semiconductor portion having the second conductivity type ([Pg 10 lines 3-11 in machine translation], figure 7a, one first isolation feature #56 includes a first doped semiconductor portion #56. In a embodiment, the first doped semiconductor portion #56 has the second conductivity type of P-Type).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified by Jain to include at least one first isolation feature including a first doped semiconductor portion as taught by Chen in order to increase device versatility, enhance the devices efficiency, and to promote the process integration.
Regarding claim 11. Lai as modified lacks wherein a dopant concentration of the doped semiconductor portion is less than a dopant concentration of each of the two source/drain portions by at least two to four orders of magnitude.
Chen discloses wherein a dopant concentration of the doped semiconductor portion is less than a dopant concentration of each of the two source/drain portions by at least two to four orders of magnitude ([pg 10, lines 26-30 from the Machine Translation], figure 7a, the dopant concentration of the first doped semiconductor portion #56 is less than the dopant concentration of the two source/drain portion #60 by two orders of magnitude (as described exactly)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified to include wherein a difference between a dopant concentration of the first doped semiconductor portion and a dopant concentration of the two source/drain portions is at two orders of magnitude as taught by Chen in order to enhance carrier mobility, reduce defect formation and for better process control.
Regarding claim 12. Lai as modified discloses wherein the insulating portion is formed to be spaced apart from the channels ([0019], figure 16, the insulating portion #222 is formed to be spaced apart from the channels #208).
Regarding claim 15. Lai as modified lacks wherein the insulating portion includes silicon oxide, silicon oxycarbide, silicon oxynitride, silicon nitride, silicon oxycarbon nitride, or combinations thereof.
Jain discloses wherein the insulating portion includes silicon oxide, silicon oxycarbide, silicon oxynitride, silicon nitride, silicon oxycarbon nitride, or combinations thereof ([0020], figure 1, the insulating portion #102 includes silicon oxide as a material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified to include wherein the insulating portion includes silicon oxide, silicon oxycarbide, silicon oxynitride, silicon nitride, silicon oxycarbon nitride, or combinations thereof as taught by Chen in order reduce manufacturing costs, speed up the manufacturing process of the device, and for enhanced electrical insulation.
Regarding claim 16. Lai as modified discloses wherein the first conductivity type is an n-type conductivity ([0013], figure 6, forming a well region #2000 at substrate #202 with a first conductivity type of n-type dopants)
Lai as modified lacks the second conductivity type is a p-type conductivity, and the doped semiconductor portion includes a group IV semiconductor material which is doped with group III elements.
Chen discloses the second conductivity type is a p-type conductivity, and the doped semiconductor portion includes a group IV semiconductor material which is doped with group III elements ([Pg 10 lines 3-11 in machine translation], figure 7a, one first isolation feature #56 includes a first doped semiconductor portion #56. the first doped semiconductor portion #56 has the second conductivity type of P-Type and is also made of silicon (group IV material) and doped with boron (group III material)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified to include the second conductivity type is a p-type conductivity, and the doped semiconductor portion includes a group IV semiconductor material which is doped with group III elements as taught by Chen in order reduce manufacturing costs by choosing commonly used materials, reduce future device failure, and to enhance the devices processing efficiency.
Regarding claim 10 (this claim is twice rejected, but this time is using a different interpretation of the primary reference to Lai et al.). Lai discloses a method for manufacturing a semiconductor structure, comprising:
forming a well region having a first conductivity type ([0013], figure 6, forming a well region #1000 at substrate #202 with a first conductivity type of p-type dopants);
forming a channel ([0014], figure 6, forming a channel #208);
forming two source/drain portions on the well region so that the two source/drain portions are respectively located at two opposite sides of the channel, the two source/drain portions having a second conductivity type which is opposite to the first conductivity type ([0026], figure 16, forming two source/drain portions #232 on the well region #1000 so that the source/drain portions #232 are at opposite ends of the chanel #208. Also the source/drain portions #232 have a second conductivity type of n-type dopants).
Lai lacks forming at least one isolation feature including a doped semiconductor portion and an insulating portion which are respectively in contact with the well region and a corresponding one of the two source/drain portions, the doped semiconductor portion having the second conductivity type.
Jain discloses forming at least one isolation feature including an insulating portion which is respectively in contact with a corresponding one of the two source/drain portions ([0022], figure 1, one isolation feature #105/102 (specifically in section #161) includes an insulating portion #102 a corresponding one of the two source/drain portions #106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai to include forming at least one isolation feature including a doped semiconductor portion and an insulating portion as taught by Jain in order to enhance electrical insulation, improve efficiency in the source/drain portion, and to increase the devices lifetime.
Lai as modified by Jain still lacks forming at least one isolation feature including a doped semiconductor portion which is respectively in contact with the well region, the doped semiconductor portion having the second conductivity type.
Chen discloses forming at least one isolation feature including a doped semiconductor portion which is respectively in contact with the well region, the doped semiconductor portion having the second conductivity type ([Pg 4 lines 26-35 in machine translation], figure 7a, one first isolation feature #56 includes a first doped semiconductor portion #56. In a embodiment, the first doped semiconductor portion #56 has the second conductivity type of n-Type).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified by Jain to include at least one first isolation feature including a first doped semiconductor portion as taught by Chen in order to increase device versatility, enhance the devices efficiency, and to promote the process integration.
Regarding claim 17 (using the different interpretation of the primary reference Lai et al.). Lai as modified discloses wherein the first conductivity type is a p-type conductivity ([0013], figure 6, forming a well region #1000 at substrate #202 with a first conductivity type of p-type dopants).
Lai as modified lacks the second conductivity type is an n-type conductivity, and the doped semiconductor portion includes a group IV semiconductor material which is doped with group V elements
Chen discloses the second conductivity type is an n-type conductivity, and the doped semiconductor portion includes a group IV semiconductor material which is doped with group V elements ([Pg 10 lines 3-11 in machine translation], figure 7a, one first isolation feature #56 includes a first doped semiconductor portion #56. the first doped semiconductor portion #56 has the second conductivity type of n-Type and is also made of silicon (group IV material) and doped with arsenic (group V material)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified to include the second conductivity type is a p-type conductivity, and the doped semiconductor portion includes a group IV semiconductor material which is doped with group V elements as taught by Chen in order reduce manufacturing costs by choosing commonly used materials, reduce future device failure, and to enhance the devices processing efficiency.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US-20220367670-A1 referred as Lai), Jain et al. (US-20250120175-A1 referred as Jain) and Chen et al. (CN-114975249-A referred as Chen) in further view of Wu et al. (US-20220051933-A1 referred as Wu).
Regarding claim 4. Lai as modified lacks wherein the second insulating portion is in direct contact with the second well region, a thickness of the second insulating portion being greater than a thickness of the first insulating portion.
Jain discloses wherein the second insulating portion is in direct contact with the second well region ([0020], figure 1, the second insulating portion #102 (specifically in section #152) is in direct contact with the second well region #113).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai to include wherein the second insulating portion is in direct contact with the second well region as taught by Jain in order to maximize electrical insulation, reduce short circuits, and to reduce future device failure.
Lai as modified by Jain still lacks a thickness of the second insulating portion being greater than a thickness of the first insulating portion.
Wu discloses a thickness of the second insulating portion being greater than a thickness of the first insulating portion ([claim 8, figure 11, the thickness of the second insulating portion #42 is 16 nm and the thickness of the first insulating portion #43 is 15 nm. The second insulating portion #42 has a greater thickness than the first insulating portion #43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified by Jain to include a thickness of the second insulating portion being greater than a thickness of the first insulating portion as taught by Wu in order to reduce device failures in the future, distribute weight across the device, and to reduce materials used in manufacturing.
Regarding claim 5. Lai as modified lacks wherein a difference between the thickness of the second insulating portion and the thickness of the first insulating portion ranges from 0.5 nm to 3 nm.
Wu discloses wherein a difference between the thickness of the second insulating portion and the thickness of the first insulating portion ranges from 0.5 nm to 3 nm ([claim 8, figure 11, the thickness of the second insulating portion #42 is 16 nm and the thickness of the first insulating portion #43 is 15 nm. The thickness of the second insulating portion #42 has a 1 nm difference than the first insulating portion #43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lai as modified by Jain to include wherein a difference between the thickness of the second insulating portion and the thickness of the first insulating portion ranges from 0.5 nm to 3 nm as taught by Wu in order to simplify the design process, speed up the manufacturing process, and to reduce manufacturing costs.
Allowable Subject Matter
Claims 18-20 are allowed. Regarding claim 18, the prior art does not teach or render obvious implanting the two semiconductor portions with second dopants, the second dopants having a second conductivity type which is opposite to the first conductivity type; forming two insulating portions respectively on the two semiconductor portions; and forming two source/drain portions respectively on the two insulating portions such that each of the channels extends between the two source/drain portions, the two source/drain portions having the second conductivity type and in the combination as claimed.
Claims 6-9 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record but not relied upon is considered pertinent to applicants disclosure for Liaw (US-20230261090-A1) and Huang et al.(US-20230137766-A1) for the source/drain region and the channels present in the prior art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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