DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3 and 9-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claims 1 and 3, the claims recite a field effect transistor including a “variable resistance drift region” or “variable resistance region”. However, the claims do not specify the structure that causes the drift region or extended drain region to have variable resistance. For example, the claims do not recite whether the variable resistance is achieved by a gate structure, a field plate, a doped pocket, an accumulation region, a depletion-control region or any particular structural arrangement between the gate electrode and the drift/extended drain region. Therefore, it is unclear what structural features distinguish the claimed variable resistance region from an ordinary drift or extended drain region.
Regarding claim 9, the claim recites the term “semiconductor characteristics” which is indefinite as the term “characteristics” is ambiguous because it may refer to multiple different properties of a semiconductor material or region such as conductivity type, dopant concentration, carrier concentration, conductivity, resistivity, threshold-voltage behavior or another semiconductor property.
Claims 10-19 depend upon claim 9 and do not rectify the problem therefore, they are also rejected.
Regarding claim 17, the claim recites an apparatus including a primary gate structure and a secondary gate structure. However, the claim further recites that “primary gate structure and the secondary gate structure are biased by a common voltage source”. It is unclear whether this limitation recites a structural relationship such as the gates being electrically connected to the same voltage source or whether it recites an act of biasing the gate structures in which case the claim improperly mixes an apparatus with a method of using the apparatus.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kai et al. (CN 115020486 A; hereafter Kai).
Regarding claim 1, Kai teaches a field-effect transistor including a variable-resistance drift region (see e.g., the transistor structure consists of a P-well region and an N-type drift region located on a substrate. A first gate is formed on the surface of the P-well and at least two second gates spaced apart from each other along the surface of the N-type drift region.
The second gates are configured to control the electrical characteristics of the N-type drift region. When the transistor is in the off state, a voltage applied to these second gates enhances the depletion of the N-type drift region, thereby increasing the breakdown voltage of the interface region between the P-well and the N-type drift region and enabling the device to withstand higher voltages.
When the device is in the on state, a voltage applied to the second gates attracts more electrons to the surface of the N-type drift region, thereby forming a high concentration electron accumulation layer. This accumulation layer modulates the N-type drift region’s conductivity and reduces the on-resistance of the device. Accordingly, the N-type drift region has a resistance/conductivity that varies depending on the voltage applied to the second gates, Figure 2).
Regarding claim 2, Kai, as referred in claim 1, further teaches
wherein the variable-resistance drift region is controlled by a gate structure such that application of a first bias voltage to the gate structure increases the resistance of the variable-resistance drift region and application of a second bias voltage to the gate structure decreases the resistance of the variable-resistance drift region (see e.g., The second gates are configured to control the electrical characteristics of the N-type drift region. When the transistor is in the off state, a voltage applied to these second gates enhances the depletion of the N-type drift region, thereby increasing the breakdown voltage of the interface region between the P-well and the N-type drift region and enabling the device to withstand higher voltages.
When the device is in the on state, a voltage applied to the second gates attracts more electrons to the surface of the N-type drift region, thereby forming a high concentration electron accumulation layer. This accumulation layer modulates the N-type drift region’s conductivity and reduces the on-resistance of the device. Accordingly, the N-type drift region has a resistance/conductivity that varies depending on the voltage applied to the second gates, Figure 2).
Regarding claim 3, Kai teaches a field-effect transistor including an extended drain region configured to include a variable resistance region (see e.g., an LDMOS transistor structure including a substrate, a P-well region and an N-type drift region located on the substrate. A first gate formed on the surface of the P-well region and a drain region disposed in the N-type drift region at a distance form the first gate. The drain region is considered an extended drain region because the drain is laterally spaced apart from the channel/gate region by the N-type drift region. That is, the drain is not located immediately adjacent to the channel region but is extended away from the gate/channel by the intervening N-type drift region which is the typical structure of an extended drain/LDMOS transistor.
At least two second gates spaced apart from each other along the surface of the N-type drift region.
The second gates are configured to control the electrical characteristics of the N-type drift region. When the transistor is in the off state, a voltage applied to these second gates enhances the depletion of the N-type drift region, thereby increasing the breakdown voltage of the interface region between the P-well and the N-type drift region and enabling the device to withstand higher voltages.
When the device is in the on state, a voltage applied to the second gates attracts more electrons to the surface of the N-type drift region, thereby forming a high concentration electron accumulation layer. This accumulation layer modulates the N-type drift region’s conductivity and reduces the on-resistance of the device. Accordingly, the extended drain region, including the N-type drift region between the first gate and the drain, includes a region whose resistance/conductivity varies based on the voltage applied to the second gates, Figure 2).
Regarding claim 4, Kai, as referred in claim 3, further teaches
wherein a resistance of the variable resistance region is controlled by a gate structure such that application of a first bias voltage to the gate structure increases the resistance of the extended drain region and application of a second bias voltage to the gate structure decreases the resistance of the extended drain region (see e.g., The second gates are configured to control the electrical characteristics of the N-type drift region. When the transistor is in the off state, a voltage applied to these second gates enhances the depletion of the N-type drift region, thereby increasing the breakdown voltage of the interface region between the P-well and the N-type drift region and enabling the device to withstand higher voltages.
When the device is in the on state, a voltage applied to the second gates attracts more electrons to the surface of the N-type drift region, thereby forming a high concentration electron accumulation layer. This accumulation layer modulates the N-type drift region’s conductivity and reduces the on-resistance of the device. Accordingly, the extended drain region, including the N-type drift region between the first gate and the drain, includes a region whose resistance/conductivity varies based on the voltage applied to the second gates, Figure 2).
Regarding claim 5, Kai, as referred in claim 3, further teaches
wherein the field-effect transistor is an N-type extended drain metal-oxide-semiconductor transistor (see e.g., N-type LDMOS transistor structure in which drain is spaced apart from the first gate/channel region by the N-type drift region, Figure 2).
Regarding claim 7, Kai, as referred in claim 3, further teaches
wherein the field-effect transistor is an N-type laterally-diffused metal-oxide-semiconductor transistor (see e.g., N-type LDMOS transistor structure, Figure 2).
Claims 9-13 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. (US 2014/0042538 A1; hereafter Li).
Regarding claim 9, Li teaches an integrated circuit fabricated on a substrate (see e.g., Figure 2) and including:
(a) a source region fabricated within an active layer on the substrate and doped to have a first semiconductor characteristic (see e.g., n-type source region 24, Para [0039], Figure 2);
(b) a body region fabricated within the active layer adjacent to the source region and doped to have a second semiconductor characteristic (see e.g., p-type well 11/p-type epitaxial layer 10 formed adjacent the n-type source region 24, Para [0038], Figure 2);
(c) a primary gate structure formed above the body region (see e.g., a polysilicon gate 15 formed over the p-type well1/p-type epitaxial layer 10, Para [0047], Figure 2);
(d) a first drift region fabricated within the active layer adjacent the body region and doped to have a third semiconductor characteristic (see e.g., left portion of lightly doped n-type drain region 12 adjacent to the p-type well 11/p-type epitaxial layer 10, Para [0041], Figure 2);
(e) a well region fabricated within the active layer adjacent to the first drift region and doped to have a fourth semiconductor characteristic (see e.g., a moderately doped n-type region 23 adjacent the left portion of the lightly n-type doped drain region 12, Para [0043], Figure 2);
(f) a secondary gate structure formed above the well region (see e.g., Faraday shield 17 formed over the moderately doped n-type region 23, Para [0047], Figure 2);
(g) a second drift region fabricated within the active layer adjacent the well region and doped to have a fifth semiconductor characteristic; and (see e.g., right portion of the lightly n-type doped drain region 12 adjacent the moderately doped n-type region 23, Para [0043], Figure 2)
(h) a drain region fabricated within the active layer adjacent the second drift region and doped to have a sixth semiconductor characteristic (see e.g., heavily doped n-type drain region 21 adjacent the right portion of the lightly n-type doped drain region 12, Para [0043], Figure 2).
Regarding claim 10, Li, as referred in claim 9, does not explicitly teach
“wherein application of a first bias voltage to the secondary gate structure increases the resistance of the well region and application of a second bias voltage to the secondary gate structure decreases the resistance of the well region”.
However, Li teaches a similar device structure and addresses the same purpose of reducing the on-resistance while maintaining a high breakdown voltage.
Applying different bias voltages to Li’s Faraday shield/field plate would predictably alter the depletion or accumulation condition in the underlying drift region.
Accordingly, because Lee teaches a structure similar to the claimed secondary gate structure over a drift/well region, biasing Li’s Faraday shield/field plate would result in a similar outcome, namely varying the resistance of the underlying well/drift region in response to the applied voltage.
Regarding claim 11, Li, as referred in claim 9, further teaches
wherein the first and sixth semiconductor characteristics are an N+ type and the second semiconductor characteristic is a P type (see e.g., n-type heavily doped source region 24 and heavily doped n-type drain region 21, Paras [0039], [0040], Figure 2).
Regarding claim 12, Li, as referred in claim 9, further teaches
wherein the fourth semiconductor characteristic is an N type (see e.g., moderately doped n-type region 23, Para [0041], Figure 2).
Regarding claim 13, Li, as referred in claim 9, further teaches
wherein the third and fifth semiconductor characteristics are an N- type (see e.g., the left and right portions of the lightly doped n-type drain region 12, Para [0038], Figure 2).
Regarding claim 19, Li, as referred in claim 9, further teaches
wherein the integrated circuit is fabricated with a semiconductor-on-insulator process.
It is noted that the limitation “fabricated with a semiconductor-on-insulator process” is considered to be a process limitation, and since the current claim is directed to a device structure, this limitation is considered a “product by process” feature, wherein the claim is directed to the product, and no matter how the structure is actually made, it is the final product which must be determined in a claim directed to an product, and not the patentability of the process. MPEP 2113, I. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) See MPEP 2113. In the instant case, while Cho may not teach the process by which the trench hole is formed, no patentable weight is afforded to the etching to form the trench hole.
Therefore, it is maintained that Li recites the same product, regardless if achieved by a separate process.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kai et al. (CN 115020486 A; hereafter Kai).
Regarding claim 6, Kai, as referred in claim 3, does not explicitly teach
“wherein the field-effect transistor is a P-type extended drain metal-oxide-semiconductor transistor”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Kai’s N-type extended drain MOS transistor to be a P-type extended drain MOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Regarding claim 8, Kai, as referred in claim 3, does not explicitly teach
“wherein the field-effect transistor is a P-type laterally-diffused metal-oxide-semiconductor transistor”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Kai’s N-type LDMOS transistor to be a P-type LDMOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2014/0042538 A1; hereafter Li).
Regarding claim 14, Li, as referred in claim 9, does not explicitly teach
“wherein the first and sixth semiconductor characteristics are a P+ type and the second semiconductor characteristic is an N type”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Li’s N-type LDMOS transistor to be a P-type LDMOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Regarding claim 15, Li, as referred in claim 9, further teaches
“wherein the fourth semiconductor characteristic is a P type”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Li’s N-type LDMOS transistor to be a P-type LDMOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Regarding claim 16, Li, as referred in claim 9, further teaches
“wherein the third and fifth semiconductor characteristics are a P- type”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Li’s N-type LDMOS transistor to be a P-type LDMOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2014/0042538 A1; hereafter Li) in view of Wang et al. (US 2019/0288112 A1; hereafter Wang).
Regarding claim 17, Li, as referred in claim 9, does not explicitly teach
“wherein the primary gate structure and the secondary gate structure are biased by a common voltage source”.
In a similar field of endeavor Wang teaches that transistor field plates can utilize various biasing configurations, including being biased by a source voltage or a gate voltage. Biasing the field plate with a source voltage provides high-voltage devices with low on-resistance and low dynamic power dissipation making them well suited for high frequency switching applications. Conversely, biasing the metal plate with a gate voltage provides LDMOS devices a favorable low on-resistance versus high breakdown voltage ratio which is ideal for low frequency applications.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to have the primary gate structure and the secondary gate structure biased by a common voltage source based on specific device requirements such as achieve a balance of low on-resistance and high breakdown voltage for low frequency operations.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2014/0042538 A1; hereafter Li) in view of Kai et al. (CN 115020486 A; hereafter Kai).
Regarding claim 18, Li, as referred in claim 9, further teaches
wherein the primary gate structure includes a first insulating layer having a first thickness (see e.g., gate oxide layer 14 having a first thickness, Para [0012], Figure 2) and the secondary gate structure includes a second insulating layer having a second thickness (see e.g., an oxide 16 disposed under the Faraday shield 17 having a second thickness, Para [0015], Figure 2) different from the first thickness (see e.g., ).
Li does not explicitly teach
“a second insulating layer having a second thickness different from the first thickness”.
Lee shows in Figure 2 that the thickness of the oxide layer 16 under the Faraday shield is greater than the thickness of the gate oxide layer 14 under the primary gate.
In a similar field of endeavor Kai provides an express teaching for using a thicker oxide layer under a secondary gate. Kai teaches an LDMOS transistor, as shown in Figure 3, the thickness of the second gate oxide layer 360 may be greater than the thickness of the first oxide layer 320. Kai explains that a thicker layer allows a larger voltage to be applied to the second gate without causing oxide breakdown, thereby improving breakdown voltage. Kai also teaches that applying a larger voltage to the second gates in the on state reduces the on-resistance.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to provide Li’s oxide layer under the Faraday shield/secondary gate with a greater thickness than the oxide layer under the primary gate, as taught by Kai, in order to allow a higher secondary gate voltage, prevent oxide breakdown, improve breakdown voltage and reduce on-resistance.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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