DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on July 21, 2026. Claims 1-4, 9 and 11-17 have been amended. No new claims have been added. Claims 20-34 have been canceled. Currently, claims 1-19 are pending.
Applicant’s amendment to claims 1, 3, 9 and 17 successfully overcomes the 112(b) rejection of claims 1, 3, 9 and 17 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11 and 14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 11 and 14, claim 11 recites an N+ source region and a P drain region for a transistor. Claim 14 recites a P+ source region and an N drain region for the transistor.
However, there is no support for a transistor with oppositely doped source and drain regions in the disclosure. The disclosed n-type transistor describes source and drain regions having same n-type conductivity and the disclosed p-type transistor describes source and drain regions having same p-type conductivity.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 11-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 4, the claim recites, “the gate structure” which is indefinite and lacks antecedent basis.
Regarding claims 11-16, claim 9 recites the source region doped with first dopant, first drift region doped with third dopant, well region doped with fourth dopant, second drift region doped with fifth dopant and drain region doped with sixth dopant.
However, claims 11-16 recite specific conductivity types for example N+, P-type, N-type for these same regions. The structural relationship between the numerical dopants to the specific conductivity type is unclear.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2014/0042538 A1; hereafter Li) in view of Palacios et al. (US 2014/0070228 A1; hereafter Palacios).
Regarding claim 1, Li teaches a field-effect transistor (see e.g., Figure 2) including
a body (see e.g., p-type well 11/p-type epitaxial layer 10 formed adjacent the n-type source region 24, Para [0038], Figure 2),
a drain (see e.g., heavily doped n-type drain region 21 adjacent the right section of the lightly n-type doped drain region 12, Para [0043], Figure 2),
at least one extended drift region located between the body and the drain, and (see e.g., left and right sections of the lightly n-type doped drain region 12 with the moderately doped n-type region 23 in between. These said sections are between the n-type drain region 21 and the p-type well 11/p-type epitaxial layer 10, Para [0043], Figure 2)
a variable-resistance drift region including a secondary transistor having a doped well located adjacent the at least one extended drift region and between the drain and the body (see e.g., a moderately doped n-type region 23 in between the right and left sections of the lightly n-type doped drain region 12. This region 23 lies between the n-type drain region 21 and p-type well 11/ p-type epitaxial layer 10. A conductive Faraday shield 17 is disposed over insulating layer 16 and above the n-type doped region 23. This setup lets the Faraday shield 17 act as a conductive field-control electrode over the doped region 23, matching the structure of the secondary transistor, Paras [0014], [0015], [0043], Figure 2),
the doped well being differently doped than the at least one extended drift region (see e.g., the n-type drain region 12 is lightly doped while the n-type region 23 is moderately doped, Paras [0038], [0041], Figure 2),
Li does not explicitly teach
“the secondary transistor including a secondary gate structure configured to be variably biased”.
In a similar field of endeavor Palacios teaches a transistor, as shown in Figure 2I, having a gate and a separate field plate which maybe maintained at a fixed voltage, set to a variable voltage, allowed to have a floating voltage or electrically connected to the gate or source such that the field plate is at the same voltage as the gate or source electrodes. It would have been obvious to configure the Faraday shield 17 of Li to receive a variable bias voltage as taught by Palacios, thereby configuring the Faraday shield 17 as a secondary gate structure capable of variably controlling the electric field in the underlying drain-side doped region 23.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement the secondary transistor including a secondary gate structure configured to be variably biased in order to control the electric field distribution and depletion of the underlying drain side semiconductor region and thereby improve the trade off between breakdown voltage performance and the on-state resistance.
Regarding claim 2, Li, as modified by Palacios, teaches the limitations of claim 1 as mentioned above. Li does not explicitly teach
“wherein the application of a first bias voltage to the secondary gate structure increases the resistance of the variable-resistance drift region and application of a second bias voltage to the secondary gate structure decreases the resistance of the variable-resistance drift region”.
In a similar field of endeavor Palacios teaches a transistor, Figure 2I, having a gate and a separate field plate which may be maintained at a fixed voltage, set to a variable voltage, allowed to have a floating voltage or electrically connected to the gate or source such that the field plate is at the same voltage as the gate or source electrodes. It would have been obvious to configure the Faraday shield 17 of Li to receive a variable bias voltage as taught by Palacios, in order to vary the electric field condition and carrier distribution in the underlying doped/drift region 23.
It would have been obvious to one skilled in the art to apply varying bias voltages to achieve different degrees of depletion and resulting resistance states, as greater depletion yields higher resistance while a reduced depletion lowers resistance, representing a predictable use of a variable bias control electrode to selectively manage on-resistance and maintain desired breakdown characteristics.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement wherein the application of a first bias voltage to the secondary gate structure increases the resistance of the variable-resistance drift region and application of a second bias voltage to the secondary gate structure decreases the resistance of the variable-resistance drift region in order to selectively control the conductivity/on-resistance of the drift region while maintaining the desired breakdown voltage characteristics.
Regarding claim 3, Li teaches a field-effect transistor (see e.g., Figure 2) including
a body (see e.g., p-type well 11/p-type epitaxial layer 10 formed adjacent the n-type source region 24, Para [0038], Figure 2),
a drain, and (see e.g., heavily doped n-type drain region 21 adjacent the right section of the lightly n-type doped drain region 12, Para [0043], Figure 2)
an extended drift region between the drain and the body configured to include a variable resistance region (see e.g., left and right sections of the lightly n-type doped drain region 12 with the moderately doped n-type region 23 in between. These said sections are between the n-type drain region 21 and the p-type well 11/p-type epitaxial layer 10, Para [0043], Figure 2),
the variable resistance region including a doped well and a secondary gate structure adjacent the doped well (see e.g., a moderately doped n-type region 23 in between the right and left sections of the lightly n-type doped drain region 12. A conductive Faraday shield 17 is disposed over insulating layer 16 and above the n-type doped region 23. This setup lets the Faraday shield 17 act as a conductive field-control electrode over the doped region 23, matching the structure of the secondary transistor, Paras [0014], [0015], [0043], Figure 2),
the doped well being differently doped than the extended drift region (see e.g., the n-type drain region 12 is lightly doped while the n-type region 23 is moderately doped, Paras [0038], [0041], Figure 2).
Li does not explicitly teach
“a secondary gate structure … configured to be variably biased,”
In a similar field of endeavor Palacios teaches a transistor, Figure 2I, having a gate and a separate field plate which may be maintained at a fixed voltage, set to a variable voltage, allowed to have a floating voltage or electrically connected to the gate or source such that the field plate is at the same voltage as the gate or source electrodes. It would have been obvious to configure the Faraday shield 17 of Li to receive a variable bias voltage as taught by Palacios, such that the Faraday shield 17 functions as a variably biased secondary gate structure adjacent doped region 23.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement a secondary gate structure … configured to be variably biased in order to permit active adjustment of the electric field distribution and carrier concentration in the drain-side semiconductor region thereby allowing control of the electrical resistance and other operating characteristics of the extended drift region.
Regarding claim 4, Li, as modified by Palacios, teaches the limitations of claim 3 as mentioned above. Lee does not explicitly teach
“wherein a resistance of the variable resistance region is controlled by the gate structure such that application of a first bias voltage to the gate structure increases the resistance of the extended drift drain region and application of a second bias voltage to the gate structure decreases the resistance of the extended drift drain region.”
In a similar field of endeavor Palacios teaches a transistor, Figure 2I, having a gate and a separate field plate which may be maintained at a fixed voltage, set to a variable voltage, allowed to have a floating voltage or electrically connected to the gate or source such that the field plate is at the same voltage as the gate or source electrodes. It would have been obvious to configure the Faraday shield 17 of Li to receive a variable bias voltage as taught by Palacios, in order to vary the electric field condition and carrier distribution in the underlying doped/drift region 23.
It would have been obvious to one skilled in the art to apply varying bias voltages to achieve different degrees of depletion and resulting resistance states, as greater depletion yields higher resistance while a reduced depletion lowers resistance, representing a predictable use of a variable bias control electrode to selectively manage on-resistance and maintain desired breakdown characteristics.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement wherein a resistance of the variable resistance region is controlled by the gate structure such that application of a first bias voltage to the gate structure increases the resistance of the extended drift drain region and application of a second bias voltage to the gate structure decreases the resistance of the extended drift drain region in order to selectively control the conductivity/on-resistance of the drift region while maintaining the desired breakdown voltage characteristics.
Regarding claim 5, Li, as modified by Palacios, teaches the limitations of claim 3 as mentioned above. Li further teaches
wherein the field-effect transistor is an N-type extended drain metal-oxide-semiconductor transistor (see e.g., N-type laterally diffused metal oxide semiconductor (LDMOS) having an extended drift region, Figure 2).
Regarding claim 6, Li, as modified by Palacios, teaches the limitations of claim 3 as mentioned above. Li does not explicitly teach
“wherein the field-effect transistor is a P-type extended drain metal-oxide-semiconductor transistor”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Li’s N-type extended drain MOS transistor to be a P-type extended drain MOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Regarding claim 7, Li, as modified by Palacios, teaches the limitations of claim 3 as mentioned above. Li further teaches
wherein the field-effect transistor is an N-type laterally-diffused metal-oxide-semiconductor transistor (see e.g., N-type laterally diffused metal oxide semiconductor (LDMOS) having an extended drift region, Figure 2).
Regarding claim 8, Li, as modified by Palacios, teaches the limitations of claim 3 as mentioned above. Li does not explicitly teach
“wherein the field-effect transistor is a P-type laterally-diffused metal-oxide-semiconductor transistor”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Li’s N-type LDMOS transistor to be a P-type LDMOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Regarding claim 9, Li teaches an integrated circuit fabricated on a substrate (see e.g., Figure 2) and including:
(a) a source region fabricated within an active layer on the substrate and doped with a first dopant (see e.g., n-type source region 24, Para [0039], Figure 2);
(b) a body region fabricated within the active layer adjacent to the source region and doped with a second dopant (see e.g., p-type well 11/p-type epitaxial layer 10 formed adjacent the n-type source region 24, Para [0038], Figure 2);
(c) a primary gate structure formed above the body region (see e.g., a polysilicon gate 15 formed over the p-type well1/p-type epitaxial layer 10, Para [0047], Figure 2);
(d) a first drift region fabricated within the active layer adjacent the body region and doped with a third dopant (see e.g., left portion of lightly doped n-type drain region 12 adjacent to the p-type well 11/p-type epitaxial layer 10, Para [0041], Figure 2);
(e) a well region fabricated within the active layer adjacent to the first drift region and doped with a fourth dopant (see e.g., a moderately doped n-type region 23 adjacent the left portion of the lightly n-type doped drain region 12, Para [0043], Figure 2);
(f) a secondary gate structure formed above the well region (see e.g., A conductive Faraday shield 17 is disposed over insulating layer 16 and above the n-type doped region 23. This setup lets the Faraday shield 17 act as a conductive field-control electrode over the doped region 23, matching the structure of the secondary transistor, Para [0047], Figure 2);
(g) a second drift region fabricated within the active layer adjacent the well region and doped with a fifth dopant; and (see e.g., right portion of the lightly n-type doped drain region 12 adjacent the moderately doped n-type region 23, Para [0043], Figure 2)
(h) a drain region fabricated within the active layer adjacent the second drift region and doped with a sixth dopant (see e.g., heavily doped n-type drain region 21 adjacent the right portion of the lightly n-type doped drain region 12, Para [0043], Figure 2);
wherein the well region is differently doped than the first drift region and the second drift region (see e.g., the n-type drain region 12 is lightly doped while the n-type region 23 is moderately doped, Paras [0038], [0041], Figure 2).
Li does not explicitly teach
“a secondary gate structure … configured to be coupled to a variable bias voltage source”
In a similar field of endeavor Palacios teaches a transistor, Figure 2I, having a gate and a separate field plate which may be maintained at a fixed voltage, set to a variable voltage, allowed to have a floating voltage or electrically connected to the gate or source such that the field plate is at the same voltage as the gate or source electrodes. It would have been obvious to configure the Faraday shield 17 of Li to receive a variable bias voltage as taught by Palacios, such that the Faraday shield 17 functions as a variably biased secondary gate structure adjacent doped region 23.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement a secondary gate structure … configured to be coupled to a variable bias voltage source in order to permit active adjustment of the electric field distribution and carrier concentration in the drain-side semiconductor region thereby allowing control of the electrical resistance and other operating characteristics of the extended drift region.
Regarding claim 10, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li does not explicitly teach
“wherein application of a first bias voltage to the secondary gate structure increases the resistance of the well region and application of a second bias voltage to the secondary gate structure decreases the resistance of the well region”.
In a similar field of endeavor Palacios teaches a transistor, Figure 2I, having a gate and a separate field plate which may be maintained at a fixed voltage, set to a variable voltage, allowed to have a floating voltage or electrically connected to the gate or source such that the field plate is at the same voltage as the gate or source electrodes. It would have been obvious to configure the Faraday shield 17 of Li to receive a variable bias voltage as taught by Palacios, in order to vary the electric field condition and carrier distribution in the underlying doped/drift region 23.
It would have been obvious to one skilled in the art to apply varying bias voltages to achieve different degrees of depletion and resulting resistance states, as greater depletion yields higher resistance while a reduced depletion lowers resistance, representing a predictable use of a variable bias control electrode to selectively manage on-resistance and maintain desired breakdown characteristics.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement wherein application of a first bias voltage to the secondary gate structure increases the resistance of the well region and application of a second bias voltage to the secondary gate structure decreases the resistance of the well region in order to selectively control the conductivity/on-resistance of the drift region while maintaining the desired breakdown voltage characteristics.
Regarding claim 11, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li further teaches
wherein the source region is doped to be N+ type and the drain region is doped to be P type (see e.g., n-type heavily doped source region 24 and heavily doped n-type drain region 21, Paras [0039], [0040], Figure 2).
Regarding claim 12, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li further teaches
wherein the well region fabricated within the active layer adjacent to the first drift region is doped to be N type (see e.g., moderately doped n-type region 23, Para [0041], Figure 2).
Regarding claim 13, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li further teaches
wherein the first drift region and the second drift region are doped to be N- type (see e.g., the left and right sections of the lightly doped n-type drain region 12, Para [0038], Figure 2).
Regarding claim 14, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li does not explicitly teach
“wherein the source region is doped to be P+ type and the drain region is doped to be N type.”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Li’s N-type LDMOS transistor to be a P-type LDMOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Regarding claim 15, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li does not explicitly teach
“wherein the well region fabricated within the active layer adjacent to the first drift region is doped to be a P type”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Li’s N-type LDMOS transistor to be a P-type LDMOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Regarding claim 16, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li does not explicitly teach
“first drift region and the second drift region are doped to be P- type”.
However, it would have been obvious to one skilled in the at the time the invention was effectively filed to modify Li’s N-type LDMOS transistor to be a P-type LDMOS transistor by reversing the conductivity types of the corresponding semiconductor regions. N-type and P-type MOS transistors are well known complementary variants of each other and selecting one conductivity type over the other would have been a predictable design choice depending on the intended circuit application, desired polarity of operation, and integration with other devices in an IC.
Regarding claim 17, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li does not explicitly teach
“wherein the primary gate structure and the secondary gate structure are configured to be coupled to a common bias voltage source”.
In a similar field of endeavor Palacios teaches a transistor, Figure 2I, having a gate and a separate field plate which may be maintained at a fixed voltage, set to a variable voltage, allowed to have a floating voltage or electrically connected to the gate or source such that the field plate is at the same voltage as the gate or source electrodes. It would have been obvious to configure the Faraday shield 17 of Li to be electrically connected to primary gate 15 as taught by Palacios such that the primary gate structure and secondary gate structure are coupled to a common bias voltage source.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement wherein the primary gate structure and the secondary gate structure are configured to be coupled to a common bias voltage source as it is a known arrangement for controlling the electric field distribution in the semiconductor region of the transistor.
Regarding claim 19, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li further teaches
wherein the integrated circuit is fabricated with a semiconductor-on-insulator process.
It is noted that the limitation “fabricated with a semiconductor-on-insulator process” is considered to be a process limitation, and since the current claim is directed to a device structure, this limitation is considered a “product by process” feature, wherein the claim is directed to the product, and no matter how the structure is actually made, it is the final product which must be determined in a claim directed to an product, and not the patentability of the process. MPEP 2113, I. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) See MPEP 2113. In the instant case, while Cho may not teach the process by which the trench hole is formed, no patentable weight is afforded to the etching to form the trench hole.
Therefore, it is maintained that Li recites the same product, regardless if achieved by a separate process.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2014/0042538 A1; hereafter Li) in view of Palacios et al. (US 2014/0070228 A1; hereafter Palacios) and further in view Kai et al. (CN 115020486 A; hereafter Kai).
Regarding claim 18, Li, as modified by Palacios, teaches the limitations of claim 9 as mentioned above. Li further teaches
wherein the primary gate structure includes a first insulating layer having a first thickness (see e.g., gate 15 includes a gate oxide layer 14 having a first thickness, Para [0012], Figure 2) and the secondary gate structure includes a second insulating layer having a second thickness (see e.g., an oxide 16 disposed under the Faraday shield 17 having a second thickness, Para [0015], Figure 2).
Li does not explicitly teach
“a second insulating layer having a second thickness different from the first thickness”.
Li shows in Figure 2 that the thickness of the oxide layer 16 under the Faraday shield is greater than the thickness of the gate oxide layer 14 under the primary gate.
In a similar field of endeavor Kai provides an express teaching for using a thicker oxide layer under a secondary gate. Kai teaches an LDMOS transistor, as shown in Figure 3, the thickness of the second gate oxide layer 360 may be greater than the thickness of the first oxide layer 320. Kai explains that a thicker layer allows a larger voltage to be applied to the second gate without causing oxide breakdown, thereby improving breakdown voltage. Kai also teaches that applying a larger voltage to the second gates in the on state reduces the on-resistance.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to provide Li’s oxide layer under the Faraday shield/secondary gate with a greater thickness than the oxide layer under the primary gate, as taught by Kai, in order to allow a higher secondary gate voltage, prevent oxide breakdown, improve breakdown voltage and reduce on-resistance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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