DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as lacking antecedent basis for the limitations, "the gate structure wraps around and over each nanostructure of the plurality of nanostructures” (Claim 2, Lines 2-3; and Claim 9, Lines 2-3). It is unclear the term, “the gate structure”, is “a gate stack" (Claim 1, Line 2; and Claim 8, Line 4) or a new structure. Examiner interprets “the gate structure wraps around and over each nanostructure of the plurality of nanostructures” to mean that “the gate stack wraps around and over each nanostructure of the plurality of nanostructures”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, and 6-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tak et al. (US 2017/0221893) (hereafter Tak).
Regarding claim 1, Tak discloses a semiconductor structure comprising:
a gate stack 650 (Fig. 10B, paragraph 0167) over a channel region (NSS in Fig. 10B, paragraph 0168);
a source/drain feature 662 (Fig. 10B, paragraph 0180) coupled to the channel region (NSS in Fig. 10B);
an L-shaped gate spacer 634 (Fig. 10B, paragraph 0182) extending along a sidewall of the gate stack 650 (Fig. 10B);
an etch stop layer (638 and 636 in Fig. 10B, paragraph 0182) continuously extending along a sidewall of the L-shaped gate spacer 634 (Fig. 10B) and a top surface of the source/drain feature 662 (Fig. 10B);
a dielectric layer (672 and 674 in Fig. 10B, paragraph 0196) over the etch stop layer (638 and 636 in Fig. 10B); and
a source/drain contact 690 (Fig. 10B, paragraph 0197) extending through the dielectric layer (672 and 674 in Fig. 10B) and the etch stop layer (638 and 636 in Fig. 10B) to electrically couple to the source/drain feature 662 (Fig. 10B).
Regarding claim 2, Tak further discloses the semiconductor structure of claim 1, wherein the channel region (NSS in Fig. 10B) comprises a plurality of nanostructures (N1, N2, and N3 in Fig. 10B, paragraph 0198), and the gate structure 650 (Fig. 10B) wraps around and over each nanostructure of the plurality of nanostructures (N1, N2, and N3 in Fig. 10B).
Regarding claim 4, Tak further discloses the semiconductor structure of claim 1, wherein the source/drain feature 662 (Fig. 10B) is adjacent to the gate stack 650 (Fig. 10B) along a first direction (horizontal direction in Fig. 10B), the L-shaped gate spacer 634 (Fig. 10B) comprises a vertical portion (vertical portion of 634 in Fig. 10B) extending along an upper portion of the sidewall of the gate stack 650 (Fig. 10B) and a horizontal portion (horizontal portion of 634 in Fig. 10B) extending along a lower portion of the sidewall of the gate stack 650 (Fig. 10B), wherein, a thickness of the vertical portion (vertical portion of 634 in Fig. 10B) along the first direction (horizontal direction in Fig. 10B) is different than a thickness of the horizontal portion (horizontal portion of 634 in Fig. 10B) along the first direction.
Regarding claim 6, Tak further discloses the semiconductor structure of claim 4, wherein a portion of the etch stop layer (638 and 636 in Fig. 10B) is disposed on a top surface of the horizontal portion of the L-shaped gate spacer 634 (Fig. 10B).
Regarding claim 7, Tak further discloses the semiconductor structure of claim 4, wherein a portion of the dielectric layer (672 and 674 in Fig. 10B) is disposed directly over the horizontal portion of the L-shaped gate spacer 634 (Fig. 10B).
Regarding claim 8, Tak discloses a semiconductor structure, comprising:
a fin-shaped active region (FA, 606, 662, and NSS in Fig. 10B) comprising a channel region (NSS in Fig. 10B, paragraph 0168) and a source/drain region 662A (Fig. 10B, paragraph 0181);
a source/drain feature 662B (Fig. 10B, paragraph 0181) in and over the source/drain region 662A (Fig. 10B);
a gate stack 650 (Fig. 10B, paragraph 0167) over the channel region (NSS in Fig. 10B) of the fin-shaped active region (FA, 606, 662, and NSS in Fig. 10B);
a gate spacer 634 (Fig. 10B, paragraph 0182) extending along a sidewall of the gate stack 650 (Fig. 10B);
a dielectric layer (636 and 638 in Fig. 10B, paragraph 0182) over the source/drain feature 662B (Fig. 10B) and adjacent to the gate spacer 634 (Fig. 10B) and having a top surface coplanar with a topmost surface of the gate spacer 634 (Fig. 10B);
a source/drain contact 690 (Fig. 10B, paragraph 0197) extending through the dielectric layer (636 and 638 in Fig. 10B) to electrically couple to the source/drain feature 662B (Fig. 10B), wherein a portion of the dielectric layer (636 and 638 in Fig. 10B) is disposed directly over the gate spacer 634 (Fig. 10B).
Regarding claim 9, Tak further discloses the semiconductor structure of claim 8, wherein the channel region (NSS in Fig. 10B, paragraph 0168) comprises a plurality of nanostructures (N1, N2, and N3 in Fig. 10B, paragraph 0198), and the gate structure 650 (Fig. 10B) wraps around and over each nanostructure of the plurality of nanostructures (N1, N2, and N3 in Fig. 10B).
Regarding claim 10, Tak further discloses the semiconductor structure of claim 8, wherein the gate spacer 634 (Fig. 10B, paragraph 0182) has a L-shaped profile and comprises a vertical portion (vertical portion of 634 in Fig. 10B) extending along an upper portion of the gate stack 650 (Fig. 10B) and a horizontal portion (horizontal portion of 634 in Fig. 10B) extending along a lower portion of the gate stack 650 (Fig. 10B), wherein, a width of the vertical portion (vertical portion of 634 in Fig. 10B) is less than a width of the horizontal portion (horizontal portion of 634 in Fig. 10B).
Regarding claim 11, Tak further discloses the semiconductor structure of claim 8, wherein the dielectric layer (636 and 638 in Fig. 10B) is a first dielectric layer (636 and 638 in Fig. 10B), the semiconductor structure further comprises: a second dielectric layer 674 (Fig. 10B, paragraph 0196) on the first dielectric layer (636 and 638 in Fig. 10B), wherein a composition (see paragraph 0196, wherein “silicon oxide layer”) of the second dielectric layer 674 (Fig. 10B) is different than a composition (see paragraph 0187, wherein “silicon nitride layer”) of the first dielectric layer (636 and 638 in Fig. 10B).
Regarding claim 12, Tak further discloses the semiconductor structure of claim 11, wherein a portion of the second dielectric layer 674 (Fig. 10B) is disposed directly over a portion of the gate spacer 634 (Fig. 10B).
Regarding claim 13, Tak (utilized different element for a second dielectric layer as applied in claim 11 in the above) further discloses the semiconductor structure of claim 8, wherein the dielectric layer (636 and 638 in Fig. 10B) is a first dielectric layer (636 and 638 in Fig. 10B), the semiconductor structure further comprises: a second dielectric layer 672 (Fig. 10B, paragraph 0196) on the first dielectric layer (636 and 638 in Fig. 10B), wherein a composition (see paragraph 0196, wherein “silicon oxide layer”) of the second dielectric layer 672 (Fig. 10B) is different than a composition (see paragraph 0187, wherein “silicon nitride layer”) of the first dielectric layer (636 and 638 in Fig. 10B); and
wherein a top surface the second dielectric layer 672 (Fig. 10B) is coplanar with the topmost surface of the gate spacer 634 (Fig. 10B).
Regarding claim 14, Tak further discloses the semiconductor structure of claim 13, wherein the top surface the second dielectric layer 672 (Fig. 10B) spans a first width, a bottom surface the second dielectric layer 672 (Fig. 10B) spans a second width less than the first width.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao et al. (US 2019/0131176) (hereafter Liao).
Regarding claim 1, Liao discloses a semiconductor structure comprising:
a gate stack 94 (Fig. 18B, paragraph 0061) over a channel region (52 and 56 in Fig. 18B, paragraph 0036);
a source/drain feature 82 (Fig. 18B, paragraph 0048) coupled to the channel region (52 and 56 in Fig. 18B);
an L-shaped gate spacer (element number is not shown in Fig. 18B but see 80A and 80B in Fig. 11B, paragraph 0047) extending along a sidewall of the gate stack 94 (Fig. 18B);
an etch stop layer 87 (Fig. 18B, paragraph 0058) continuously extending along a sidewall of the L-shaped gate spacer (element number is not shown in Fig. 18B but see 80A and 80B in Fig. 11B) and a top surface of the source/drain feature 82 (Fig. 18B);
a dielectric layer 88 (Fig. 18B, paragraph 0058) over the etch stop layer 87 (Fig. 18B); and
a source/drain contact 104 (Fig. 18B, paragraph 0064) extending through the dielectric layer 88 (Fig. 18B) and the etch stop layer 87 (Fig. 18B) to electrically couple to the source/drain feature 82 (Fig. 18B).
Regarding claim 3, Liao further discloses the semiconductor structure of claim 1, wherein the channel region (52 and 56 in Fig. 18B) comprises a fin-shaped semiconductor layer protruding from a substrate 50 (Fig. 18B, paragraph 0027).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tak as applied to claim 4 above, and further in view of Shima (US 2007/0196972) (hereafter Shima).
Regarding claim 5, Tak discloses the semiconductor structure of claim 4, however Tak does not disclose a ratio of a thickness of the vertical portion to a thickness of the horizontal portion is about 0.2 to about 0.9.
Shima discloses a ratio of a thickness (horizontal length of R1 in Fig. 2, wherein “15nm”) of the vertical portion R1 (Fig. 2) to a thickness (horizontal length of R2 in Fig. 2, wherein “30nm”) of the horizontal portion is about 0.2 to about 0.9 (see Fig. 2, wherein ratio is 0.5 (15 nm / 30 nm)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tak to form a ratio of a thickness of the vertical portion to a thickness of the horizontal portion is about 0.2 to about 0.9, as taught by Shima, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tak et al. (US 2017/0221893) (hereafter Tak), in view of Liao et al. (US 2019/0131176) (hereafter Liao).
Regarding claim 15, Tak discloses a semiconductor structure, comprising:
a gate stack 650 (Figs. 10A and 10B, paragraph 0167) over a substrate 602 (Fig. 10B, paragraph 0164) and extending lengthwise along a first direction (vertical direction in Fig. 10A; and stacking direction in Fig. 10B);
a gate spacer 634 (Fig. 10B, paragraph 0182) extending along a sidewall of the gate stack 650 (Fig. 10B), wherein the gate spacer 634 (Fig. 10B) comprises:
a top portion (top portion of 634 in Fig. 10B) having a first uniform thickness (horizontal length of top portion of 634 in Fig. 10B) along a second direction (horizontal direction in Fig. 10B) substantially perpendicular to the first direction (stacking direction in Fig. 10B), and a bottom portion (bottom portion of 634 in Fig. 10B) having a second uniform thickness (horizontal length of bottom portion of 634 in Fig. 10B) along the second direction (horizontal direction in Fig. 10B), wherein the second uniform thickness (horizontal length of bottom portion of 634 in Fig. 10B) is greater than the first uniform thickness (horizontal length of top portion of 634 in Fig. 10B).
Tak does not disclose the bottom portion has a height greater than the second uniform thickness.
Liao discloses the bottom portion (element number is not shown in Fig. 18B but see horizontal portion of 58, 80A and 80B in Fig. 10B) in has a height (see paragraph 0038, wherein the thickness of 58 is between about 11 nm and about 15 nm; and see paragraph 0043, wherein the thickness of 80A is between about 3 nm and about 5 nm; the thickness of 80B is between about 3 nm and about 5 nm; and the thickness of 80C is between about 4 nm and about 6 nm. Therefore, the height of 58, 80A, and 80B is between about 17 nm (11 nm + 3 nm + 3 nm) and about 25 nm (15 nm + 5 nm + 5 nm) and the second uniform thickness of 80A and 80B is between about 10 nm (3 nm + 3 nm + 4 nm) and about 16 nm (5 nm + 5 nm + 6 nm)) greater than the second uniform thickness.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tak to form the bottom portion has a height greater than the second uniform thickness, as taught by Liao, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 16, Tak in view of Liao discloses the semiconductor structure of claim 15, however Tak does not disclose a ratio of the first uniform thickness to the second uniform thickness is about 0.2 to about 0.9.
Liao discloses a ratio (see paragraph 0043, wherein the thickness of 80A is between about 3 nm and about 5 nm; the thickness of 80B is between about 3 nm and about 5 nm; and the thickness of 80C is between about 4 nm and about 6 nm. Therefore, a ratio of the first uniform thickness (horizontal length of top portion of 80A and 80B is between about 6 nm (3 nm + 3 nm) and about 10 nm (5 nm + 5 nm)) to the second uniform thickness (horizontal length of bottom portion of 80A and 80B is between about 10 nm (3 nm + 3 nm + 4 nm) and about 16 nm (5 nm + 5 nm + 6 nm)) of the first uniform thickness (element number is not shown in Fig. 18B but see horizontal length of upper portion of 80A and 80B in Fig. 10B) to the second uniform thickness (element number is not shown in Fig. 18B but see horizontal length of lower portion of 80A and 80B in Fig. 10B) is about 0.6 (6 nm / 10 nm) to about 0.625 (10 nm / 16 nm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tak to form a ratio of the first uniform thickness to the second uniform thickness is about 0.2 to about 0.9, as taught by Liao, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 17, Tak further discloses the semiconductor structure of claim 15, further comprising: a plurality of nanostructures (N1, N2, and N3 in Fig. 10B, paragraph 0198) over the substrate 602 (Fig. 10B), wherein the gate stack 650 (Fig. 10B) wraps around and over each nanostructure of the plurality of nanostructures (N1, N2, and N3 in Fig. 10B).
Regarding claim 18, Tak further discloses the semiconductor structure of claim 17, further comprising: a source/drain feature 662 (Fig. 10B, paragraph 0180) coupled to the plurality of nanostructures (N1, N2, and N3 in Fig. 10B); and a conformal etch stop layer (636 and 638 in Fig. 10B, paragraph 0182) over the gate spacer 634 (Fig. 10B) and the source/drain feature 662 (Fig. 10B), wherein the etch stop layer (636 and 638 in Fig. 10B) is on a top surface of the bottom portion of the gate spacer 634 (Fig. 10B).
Regarding claim 19, Tak further discloses the semiconductor structure of claim 18, further comprising: a dielectric layer (672 and 674 in Fig. 10B, paragraph 0196) on the etch stop layer (636 and 638 in Fig. 10B) and extending between the gate stack (leftmost 650 in Fig. 10B) and another adjacent gate stack (rightmost 650 in Fig. 10B), wherein the dielectric layer has a non-uniform width 672 (Fig. 10B).
Regarding claim 20, Tak further discloses the semiconductor structure of claim 19, wherein a portion of the dielectric layer (672 and 674 in Fig. 10B) is disposed directly over the bottom portion of the gate spacer 634 (Fig. 10B).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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