Prosecution Insights
Last updated: October 04, 2026
Application No. 18/639,994

SEMICONDUCTOR DEVICE WITH A PARTIAL SHIELDING LAYER AND A METHOD FOR MAKING THE SAME

Final Rejection §103
Filed
Apr 19, 2024
Priority
Apr 20, 2023 — CN 202310427315.3
Examiner
MUNOZ, ANDRES F
Art Unit
Tech Center
Assignee
Jcet Stats Chippac Korea Limited
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
551 granted / 722 resolved
+16.3% vs TC avg
Strong +18% interview lift
Without
With
+17.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
40 currently pending
Career history
755
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
48.9%
+8.9% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
20.8%
-19.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 722 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings were received on 8.4.2026. These drawings are acceptable. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200075502 A1, of record). Regarding claim 1, Kim discloses a method for making a semiconductor device, comprising: providing a package substrate strip (110) with multiple sets of first electronic components (50) and multiple sets of second electronic components (124) mounted thereon (Figs. 2a and 2d); forming an encapsulant layer (130) on the package substrate strip that covers the multiple sets of first electronic components (50, Figs. 2a and 2d.); forming a first shielding material (150) singulating (Figs. 2g-2h), after forming the first shielding material (150), the package substrate strip into individual semiconductor packages (156) with respective package substrates (110, Figs. 2g-2h); and forming a second shielding material (160) on the encapsulant layer by sputtering ([0033]), wherein the second shielding material at least partially overlaps with the first shielding material (Figs 2i-2k). Kim fails to disclose spray coating. Spray coating is a well-known and understood deposition technique to deposit materials such as those of the first shielding material (150, “Lid 150 can be formed by filling trench 140 with a conductive ink or paste”- [0028]). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include spray coating as claimed in Kim because spray coating was part of the ordinary capabilities of one skilled in the art and would have yielded predictable results. Regarding claim 2, Kim discloses the method of claim 1, wherein the step of forming a second shielding material (160) is conducted (in part; said interpretation is not precluded by the claim since the claim does not require said forming step to be entirely conducted after singulation) after the step of singulating the package substrate strip into individual semiconductor packages (Figs. 2j-2l), and the step of forming a second shielding material comprises: placing a deposition mask (152) to cover the second electronic components (124), the deposition mask overlapping (in a diagonal direction) at least partially with the first shielding material (150, Fig. 2i); depositing the second shielding material (160) to the semiconductor package by sputtering ([0033], Fig. 2i); and removing the deposition mask from the semiconductor package (Figs. 2i-2k). Regarding claim 3, Kim discloses the method of claim 2, wherein the deposition mask (152) overlaps (diagonally) with the first shielding material (150) on a portion of the first shielding material extending (directly or indirectly) over a respective package substrate (Fig. 2k). Regarding claim 4, Kim discloses the method of claim 2, wherein the second shielding material (160) covers (temporarily since the claim is drawn to a method which is limited by temporal changes) entirely the top surface and side surfaces of the encapsulant layer (Fig. 2i). Regarding claim 5, Kim fails to disclose the method of claim 1, wherein the step of forming an encapsulant layer comprises forming the encapsulant layer using an injection molding process. Injection molding is a well-known and commonly employed encapsulating technique used to encapsulate semiconductor devices. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include injection molding as claimed in Kim because injection molding was part of the ordinary capabilities of one skilled in the art and would have yielded predictable results, and/or, so as to enclose semiconductor devices with a well-known method. Regarding claim 6, Kim fails to disclose the method of claim 5, wherein the encapsulant layer has a shape of a truncated prism with sloping sidewalls at its periphery. It would have been obvious to one of ordinary skill in the art to arrive at the claimed shapes before the effective filing date in the method of Kim so as to avoid abrupt change in shape of the encapsulant and avoid damages to the encapsulant (e.g., delamination) because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV. Regarding claim 16, Kim discloses the method of claim 2, wherein a lower(most) end (in a thickness direction) of the deposition mask (152) rests (indirectly) against the side surface (in 102) of the encapsulant layer (140) facing towards the second electronic components (124, Fig. 2e-2f). Allowable Subject Matter Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: wherein a lower end of the deposition mask rests on the top surface of the encapsulant layer and overlaps with the first shielding material on a portion of the first shielding material above the top surface of the encapsulant layer is neither disclosed nor suggested by the prior art Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Kim et al. (US 20200075502 A1, of record) is applied to claim 1 above; see rejection above for details. The 35 USC 112 rejections of the previous Office Action have been overcome. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Andres Munoz/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Apr 19, 2024
Application Filed
May 14, 2026
Non-Final Rejection mailed — §103
Aug 04, 2026
Response Filed
Aug 17, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12713601
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
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Patent 12707950
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3y 11m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
94%
With Interview (+17.5%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 722 resolved cases by this examiner. Grant probability derived from career allowance rate.

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