DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 5 recites “including a plurality of first upper pads”. It is not clear, from this limitation, whether or not these upper pads are intended to be the same first upper pads as “a plurality of first upper pads” from line 3 of this claim, or are intended to be a different set of first upper pads. This issue renders the claim indefinite.
Claim 16, line 7 recites “including a circuit layer”. It is not clear, from this limitation, whether or not this circuit layer is intended to be the same as “a circuit layer” from line 7 of claim 15, from which this claim depends, or is intended to be a new circuit layer. This issue renders the claim indefinite.
Note that dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6-8, and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHANG (US 20210202440).
Regarding claim 1, as best the examiner is able to ascertain the claimed invention, CHANG discloses a package structure (the structure shown in fig 1I, if the device is inverted), comprising:
a molded structure (the structure comprising 110, 120 and 130, see fig 1I, para 31), comprising:
a first electronic device (the device 120 connected to 150, see fig 1I, para 31) including a plurality of first upper pads (if the device in fig 1I is inverted, the pads 127 will be upper pads, see fig 1I, para 24);
a second electronic device (fig 1I, 110, para 22) disposed side by side with the first electronic device (120 and 110 are side by side, see fig 1I), and including a plurality of first upper pads (the pads 116a of 110 which are connected to 150, see fig 1I, para 62) and a plurality of second upper pads (the pads 116a of 110 which are connected to 140, see fig 1I, para 62); and
an encapsulant (the encapsulant 130, see fig 1I, para 34) encapsulating the first electronic device and the second electronic device;
a first top die (fig 1I, 150, para 30) disposed over the molded structure (if the device of 1I is inverted, then 150 is over 130), and including a plurality of first bonding pads (the pads 184 which are connected to 120, see fig 1I, para 21) and a plurality of second bonding pads (the bonding pads 183 connected to 110, see fig 1I, para 21),
wherein the plurality of first bonding pads of the first top die are substantially aligned with and electrically connected to the plurality of first upper pads of the first electronic device respectively (184 is aligned with and connected to the pads 127 of 120, see fig 1I),
wherein the plurality of second bonding pads of the first top die are substantially aligned with and electrically connected to the plurality of first upper pads of the second electronic device respectively (the pads 183 of 150 are connected to and aligned with pads 116a of 110, see fig 1I);
a second top die (fig 1I, 140, para 21) disposed over the molded structure, and including a plurality of bonding pads (fig 1I, 182, para 21) substantially aligned with and electrically connected to the plurality of second upper pads of the second electronic device respectively (182 are aligned with and connected to pads 116a of 110, see fig 1I).
Regarding claim 3, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1, wherein a top surface of the first electronic device and a top surface of the second electronic device are substantially coplanar with a top surface of the encapsulant (top surfaces of 116b and 126b are coplanar with the top surfaces of 130 if fig 1I is inverted, see fig 1I and 1L), wherein a bottom surface of the first electronic device and a bottom surface of the second electronic device are substantially coplanar with a bottom surface of the encapsulant (bottom surfaces of 115 and 125 are coplanar with bottom surfaces of 130 if fig 1I is inverted, see fig 1I).
Regarding claim 6, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1, wherein the second electronic device further includes a bridge circuit configured to electrically connect the plurality of second bonding pads of the first top die and the plurality of bonding pads of the second top die (140 and 150 are connected by bridge die 110, see fig 1I, para 44).
Regarding claim 7, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1, wherein a portion of the second electronic device is exposed in a gap between the first top die and the second top die (a portion of 110 is located horizontally between 140 and 150, and is not covered by either of them, see fig 1I).
Regarding claim 8, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1, wherein a lateral surface of the first top die and a lateral surface of the second top die contact a top surface of the second electronic device (lateral surface of 140 and 150 are in at least indirect contact with 110, see fig 1I).
Regarding claim 18, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1, wherein a function of the first top die is different from a function of the second top die (140 and 150 can be different, heterogeneous, dies, see para 47-48).
Regarding claim 19, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 18, wherein the first top die includes a logic die, and the second top die includes a memory die (the dies 140 and 150 can be a SoC and a DRAM, see para 47-48).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 9-13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHANG (US 20210202440) in view of MALLIK (US 20200395313).
Regarding claim 2, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1.
CHANG fails to explicitly disclose a device, wherein a plurality of top surfaces of the plurality of first upper pads of the first electronic device, a plurality of top surfaces of the plurality of first upper pads of the second electronic device and a plurality of top surfaces of the plurality of second upper pads of the second electronic device are substantially coplanar with a top surface of the encapsulant.
MALLIK teaches a device, wherein a plurality of top surfaces of the plurality of first upper pads of the first electronic device, a plurality of top surfaces of the plurality of first upper pads of the second electronic device and a plurality of top surfaces of the plurality of second upper pads of the second electronic device are substantially coplanar with a top surface of the encapsulant (top surfaces of all the pads 184 of the first and second devices 130 and 140 are coplanar with the top surface of encapsulant 131, see fig 1, para 37 and 39).
CHANG and MALLIK are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG with the encapsulation configuration of MALLIK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG with the encapsulation configuration of MALLIK in order to improve alignment (see MALLIK para 40).
Regarding claim 9, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1, wherein the first electronic device further includes:
a first main portion (120 includes 125, see fig 1L, para 24);
a plurality of first through vias extending through the first main portion (the vias 126, see fig 1L, para 24); and
a plurality of first lower pads (fig 1I and 1L, 176, para 85) disposed under a bottom surface of the first main portion, and electrically connected to a plurality of lower ends of the plurality of first through vias (176 is connected to the bottom of 126, see fig 1L).
CHANG fails to explicitly disclose a device comprising a first circuit structure disposed on a top surface of the first main portion, and including a circuit layer, a plurality of first inner pads, a plurality of first inner vias and the plurality of first upper pads,
wherein the circuit layer horizontally connects the plurality of first inner pads,
wherein the plurality of first inner vias vertically connect the plurality of first inner pads and the plurality of first upper pads, and
wherein the plurality of first inner pads are electrically connected to a plurality of upper ends of the plurality of first through vias.
MALLIK teaches a device comprising a first circuit structure (the structure comprising 131, 136, 185 and 184 over 130, see fig 1, para 35) disposed on a top surface of the first main portion (131 and 136 are on a top surface of 130, see fig 1), and including a circuit layer (the layer of 131 that contacts 136, 185 and 184 along a horizontal direction, see fig 1), a plurality of first inner pads (fig 1, 136, para 36), a plurality of first inner vias (fig 1, 185, para 39) and the plurality of first upper pads (fig 1, 184, para 39),
wherein the circuit layer horizontally connects the plurality of first inner pads (131 is in contact with all of 136 along a horizontal direction, see fig 1),
wherein the plurality of first inner vias vertically connect the plurality of first inner pads and the plurality of first upper pads (105 connects 136 to 184, see fig 1B), and
wherein the plurality of first inner pads are electrically connected to a plurality of upper ends of the plurality of first through vias (136 is connected to the via 134 through 130, see fig 1, para 35).
CHANG and MALLIK are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG with the circuit structure of MALLIK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG with the circuit structure of MALLIK in order to improve alignment (see MALLIK para 40).
Regarding claim 10, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1.
CHANG fails to explicitly disclose a device, wherein the second electronic device further includes:
a second main portion;
at least one first through via disposed under the first top die, and extending through the second main portion;
a plurality of second through vias disposed under the second top die, and extending through the second main portion;
a second circuit structure disposed on a top surface of the second main portion, and including a circuit layer, a bridge circuit, at least one first inner pad, a plurality of second inner pads, a plurality of first inner vias, a plurality of second inner vias, the plurality of first upper pads and the plurality of second upper pads,
wherein the circuit layer horizontally connects the at least one first inner pad and/or the plurality of second inner pads, and
the bridge circuit electrically connects one of the plurality of first inner vias and one of the plurality of second inner vias,
wherein the plurality of first inner vias vertically connect the at least one first inner pad and the plurality of first upper pads,
wherein the at least one first inner pad is electrically connected to an upper end of the at least one first through via,
wherein the plurality of second inner vias vertically connect the plurality of second inner pads and the plurality of second upper pads,
wherein the plurality of second inner pads are electrically connected to a plurality of upper ends of the plurality of second through vias;
at least one first lower pad disposed under a bottom surface of the first main portion, and electrically connected to a lower end of the at least one first through via; and
a plurality of second lower pads disposed under the bottom surface of the second main portion, and electrically connected to a plurality of lower ends of the plurality of second through vias.
MALLIK teaches a device, wherein the second electronic device further includes:
a second main portion (fig 1, 140, para 34);
at least one first through via (the vias 144 under the left 120, see fig 1, 144, para 36) disposed under the first top die, and extending through the second main portion (see fig 1);
a plurality of second through vias (the vias 144 under the right 120, see fig 1, 144, para 36) disposed under the second top die, and extending through the second main portion;
a second circuit structure (the structure comprising 141, 146, 185 and 184, see fig 1) disposed on a top surface of the second main portion (141 is on top of 140, see fig 1), and including a circuit layer (the layer of 130 which is connected to 141, 146, 185 and 184 and extends horizontally, see fig 1), a bridge circuit (fig 1, 141, para 36), at least one first inner pad (the pads 146 under the left 120, see fig 1, 146, para 39), a plurality of second inner pads (the pads 146 under the right 120, see fig 1, 146, para 39), a plurality of first inner vias (the vias 185 under the left 120, see fig 1, para 39), a plurality of second inner vias (the vias 185 under the right 120, see fig 1, para 39), the plurality of first upper pads (the pads 184 under the left 120, see fig 1) and the plurality of second upper pads (the pads 184 under the right 120, see fig 1),
wherein the circuit layer horizontally connects the at least one first inner pad and/or the plurality of second inner pads (130 is connected to 146 and extends in a horizontal direction, see fig 1), and
the bridge circuit electrically connects one of the plurality of first inner vias and one of the plurality of second inner vias (141 is directly connected to all 144, see fig 1),
wherein the plurality of first inner vias vertically connect the at least one first inner pad and the plurality of first upper pads (146 is connected to 184 by 185, see fig 1B),
wherein the at least one first inner pad is electrically connected to an upper end of the at least one first through via (146 is connected to 144 by 141, see fig 1B),
wherein the plurality of second inner vias vertically connect the plurality of second inner pads and the plurality of second upper pads (146 is connected to 184 by 185, see fig 1B),
wherein the plurality of second inner pads are electrically connected to a plurality of upper ends of the plurality of second through vias (146 are connected to 144 by 141, see fig 1);
at least one first lower pad disposed under a bottom surface of the first main portion, and electrically connected to a lower end of the at least one first through via (the pads 143 under the left 120 connected to 144, see fig 1, para 36); and
a plurality of second lower pads disposed under the bottom surface of the second main portion, and electrically connected to a plurality of lower ends of the plurality of second through vias (the pads 143 under the right 120 connected to 144, see fig 1, para 36).
CHANG and MALLIK are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG with the circuit structure of MALLIK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG with the circuit structure of MALLIK in order to improve alignment (see MALLIK para 40).
Regarding claim 11, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1.
CHANG fails to explicitly disclose a device, wherein the molded structure further includes:
an intermediate electronic device disposed between the first electronic device and the second electronic device, and including a plurality of third upper pads; wherein the encapsulant further encapsulates the intermediate electronic device;
wherein first top die further includes a plurality of third bonding pads substantially aligned with and electrically connected to the plurality of third upper pads of the intermediate electronic device respectively.
MALLIK teaches a device, wherein the molded structure further includes:
an intermediate electronic device (the component stack 240B in cavity 235B, which is between the first electronic device 230 to the right and the second electronic device 240A to the left, see fig 2D, para 41) disposed between the first electronic device and the second electronic device, and including a plurality of third upper pads (the upper pads 184 of 240B, see fig 1 and 2D, para 39); wherein the encapsulant further encapsulates the intermediate electronic device (the encapsulant 130 also encapsulates 235B, see fig 1 and 2D);
wherein first top die further includes a plurality of third bonding pads (the pads 123 of the right 220 over 235B in fig 2D, see fig 1-2, para 39) substantially aligned with and electrically connected to the plurality of third upper pads of the intermediate electronic device respectively.
CHANG and MALLIK are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG with the intermediate device of MALLIK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG with the intermediate device of MALLIK in order to improve alignment (see MALLIK para 40).
Regarding claim 12, as best the examiner is able to ascertain the claimed invention, CHANG and MALLIK disclose the package structure of Claim 11.
CHANG fails to explicitly disclose a device, wherein a first portion of the encapsulant is disposed between the intermediate electronic device and the first electronic device, and a second portion of the encapsulant is disposed between the intermediate electronic device and the second electronic device.
MALLIK teaches a device, wherein a first portion of the encapsulant is disposed between the intermediate electronic device and the first electronic device, and a second portion of the encapsulant is disposed between the intermediate electronic device and the second electronic device (portions of encapsulant 130 are on either side of 235B, see fig 2D).
CHANG and MALLIK are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG with the encapsulant geometry of MALLIK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG with the encapsulant geometry of MALLIK in order to improve alignment (see MALLIK para 40).
Regarding claim 13, as best the examiner is able to ascertain the claimed invention, CHANG and MALLIK disclose the package structure of Claim 11.
CHANG fails to explicitly disclose a device, wherein the intermediate electronic device includes a third electronic device stacked on a fourth electronic device.
MALLIK teaches a device, wherein the intermediate electronic device includes a third electronic device stacked on a fourth electronic device (240B is a stack of memory dies on top of each other comprising at least a third and a fourth device, see fig 2D, para 44).
CHANG and MALLIK are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG with the intermediate device of MALLIK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG with the intermediate device of MALLIK in order to improve alignment (see MALLIK para 40).
Regarding claim 20, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1.
CHANG fails to explicitly disclose a device, wherein the second electronic device includes a logic die, and the first electronic device includes an interposer.
MALLIK teaches a device, wherein the second electronic device includes a logic die (140 can include logic, see fig 1A, para 36), and the first electronic device includes an interposer (130 can be an interposer, see fig 1, para 34).
CHANG and MALLIK are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG with the device functions of MALLIK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG with the device functions of MALLIK in order to improve alignment (see MALLIK para 40).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHANG (US 20210202440) in view of WU (US 20220068862).
Regarding claim 4, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1.
CHANG fails to explicitly disclose a device, wherein the first top die is electrically connected to the first electronic device and the second electronic device by hybrid bonding, wherein the second top die is electrically connected to the second electronic device by hybrid bonding.
WU teaches a device, wherein the first top die is electrically connected to the first electronic device and the second electronic device by hybrid bonding, wherein the second top die is electrically connected to the second electronic device by hybrid bonding (the bonding of 101 and 105 to the lower devices 305 by 107 can be by hybrid bonding, see fig 20, para 38).
CHANG and WU are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG with the hybrid bonding of WU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG with the hybrid bonding of WU in order to increase the density of the electrical routing (see WU para 18).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHANG (US 20210202440) in view of KIM (US 20160351506).
Regarding claim 5, as best the examiner is able to ascertain the claimed invention, CHANG discloses the package structure of Claim 1.
CHANG fails to explicitly disclose a device, wherein the first top die is electrically connected to the first electronic device and the second electronic device through a plurality of solder materials, wherein the second top die is electrically connected to the second electronic device through a plurality of solder materials.
KIM teaches a device, wherein the first top die is electrically connected to the first electronic device and the second electronic device through a plurality of solder materials, wherein the second top die is electrically connected to the second electronic device through a plurality of solder materials (the solder bumps 111, 112 and 113 comprise different materials, see fig 1 and 10, para 87-95).
CHANG and KIM are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG with the multiple solder layers of KIM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG with the multiple solder layers of KIM in order to simplify assembly and increase value (see KIM para 36).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHANG (US 20210202440) in view of MALLIK (US 20200395313) and further in view of WU (US 20220068862).
Regarding claim 14, as best the examiner is able to ascertain the claimed invention, CHANG and MALLIK disclose the package structure of Claim 13.
CHANG and MALLIK fails to explicitly disclose a device, wherein the third electronic device is electrically connected to the fourth electronic device by hybrid bonding.
WU teaches a device, wherein the third electronic device is electrically connected to the fourth electronic device by hybrid bonding (the bonding of 101 and 105 to the lower devices 305 by 107 can be by hybrid bonding, see fig 20, para 38).
CHANG, MALLIK and WU are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG and MALLIK with the hybrid bonding of WU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG and MALLIK with the hybrid bonding of WU in order to increase the density of the electrical routing (see WU para 18).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHANG (US 20210202440) in view of MALLIK (US 20200395313) and further in view of YEN (US 20230042800).
Regarding claim 15, as best the examiner is able to ascertain the claimed invention, CHANG and MALLIK disclose the package structure of Claim 13.
CHANG and MALLIK fails to explicitly disclose a device, wherein the third electronic device includes:
a third main portion;
a plurality of third through vias extending through the third main portion;
a third circuit structure disposed on a top surface of the third main portion, and including a circuit layer, a plurality of third inner pads, a plurality of third inner vias and the plurality of third upper pads,
wherein the circuit layer horizontally connects the plurality of third inner pads,
wherein the plurality of third inner vias vertically connect the plurality of third inner pads and the plurality of third upper pads,
wherein the plurality of third inner pads are electrically connected to a plurality of upper ends of the plurality of third through vias; and
a plurality of third lower pads disposed under a bottom surface of the third main portion, and electrically connected to a plurality of lower ends of the plurality of third through vias.
YEN teaches a device, wherein the third electronic device (the device 24 and associated connectors, see fig 6C, para 31) includes:
a third main portion (fig 6C, 24, para 31);
a plurality of third through vias (fig 6C, 242, para 30) extending through the third main portion;
a third circuit structure disposed on a top surface of the third main portion, and including a circuit layer (the layer of 26 horizontally around 243, see fig 6C), a plurality of third inner pads (fig 6C, 243, para 30), a plurality of third inner vias (fig 6C, 244, para 30) and the plurality of third upper pads (fig 6C, 231, para 30),
wherein the circuit layer horizontally connects the plurality of third inner pads (a layer of 26 is horizontally around 243, see fig 6C),
wherein the plurality of third inner vias vertically connect the plurality of third inner pads and the plurality of third upper pads (244 connects 243 to 231, see fig 6C),
wherein the plurality of third inner pads are electrically connected to a plurality of upper ends of the plurality of third through vias (243 is connected to 242, see fig 6C); and
a plurality of third lower pads (fig 6C, 241A, para 32) disposed under a bottom surface of the third main portion (see fig 6C), and electrically connected to a plurality of lower ends of the plurality of third through vias (see fig 6C).
CHANG, MALLIK and YEN are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG and MALLIK with the third device of YEN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG and MALLIK with the third device of YEH in order to improve heat dissipation (see YEN para 21).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHANG (US 20210202440) in view of MALLIK (US 20200395313) and further in view of ELSHERBINI (US 11217535).
Regarding claim 17, as best the examiner is able to ascertain the claimed invention, CHANG and MALLIK disclose the package structure of Claim 11.
CHANG and MALLIK fails to explicitly disclose a device, wherein the intermediate electronic device includes a cache memory chip.
ELSHERBINI teaches a device, wherein the intermediate electronic device includes a cache memory chip (the chip 114-1 can be a cache memory, see fig 1, para 121).
CHANG, MALLIK and ELSHERBINI are analogous art because they both are directed towards semiconductor package devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHANG and MALLIK with the cache memory of ELSHERBINI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHANG and MALLIK with the cache memory of ELSHERBINI in order to increase bandwidth and clock rate (see ELSHERBINI para 126).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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