CTNF 18/640,236 CTNF 92123 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Note by the Examiner 2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 3. Claims 1-14 are rejected under 35 U.S.C. 103 as obvious over Kim (US 2018/0040560 A1), hereinafter as K1, in view of Lee et al. (US 2024/0349491 A1), hereinafter as L1 4. Regarding Claim 1 , K1 discloses a semiconductor device (see in particular Figs. 1A-C, “Labeled Fig. 1B” above, and [0010] “semiconductor memory device”) , comprising: a substrate (element 100, see [0021] “substrate 100”) having a first recess region (labeled element “First Recess Region”, see [0026] “recess region 111”) ; and a first bit line structure (element BLS and SS within labeled element “First Recess Region”, see [0026] “bit line structures BLS” and [0038] “spacer structure SS”) in the first recess region (see “Labeled Fig. 1B” above) ; wherein the first bit line structure has a first spacer (element 131, see [0040] “first and second spacers 131 and 135”) , a second spacer (element 135, see [0040]) , and a third spacer (element 139, see [0039] “third spacer 139”) . K1 does not explicitly disclose wherein the first spacer, the second spacer, and the third spacer have different materials. L1 discloses wherein the first spacer, the second spacer, and the third spacer have different materials (see Fig. 3A first spacer element LS see [0034] “The line spacer LS may be formed of or include at least one of … silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN)”, the second spacer element INS see [0048] “The inner spacer INS may be formed of or include at least one of silicon oxide (SiO 2 )”, and the third spacer element OUS see [0052] “The outer spacer OUS may be formed of or include at least one of … silicon nitride (SiN)”) . The bit line multilayer spacer as taught by L1 is incorporated as the bit line multilayer spacer of K1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with K1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known bit line multilayer spacer material in a similar device for another to obtain predictable results (see L1 Fig. 3A and [0034, 0048, 0052] each of the spacers are described with a list of material which can be selected and substituted). 5. Regarding Claim 2 , K1, L1 disclose the semiconductor device of claim 1, wherein the first bit line structure contacts a first doped region in the substrate (see K1 element 1a below element “First Recess Region”, see [0025] “first and second impurity regions 1a and 1b”) . 6. Regarding Claim 3 , K1, L1 disclose the semiconductor device of claim 1, wherein a sidewall of the first recess region is inclined with respect to the substrate (see K1 “Labeled Fig. 1B”) . 7. Regarding Claim 4 , K1, L1 disclose the semiconductor device of claim 1, wherein the first spacer includes a carbon-containing material (see L1 [0034] “The line spacer LS may be formed of or include at least one of … silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN)”) . 8. Regarding Claim 5 , K1, L1 disclose the semiconductor device of claim 1, wherein the second spacer is disposed between the first spacer and the third spacer (see L1 Fig. 3A) , and a first dielectric constant of the first spacer is less than a second dielectric constant of the second spacer (see L1 [0034] “The line spacer LS may be formed of or include at least one of … silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN)” and see [0052] “The outer spacer OUS may be formed of or include at least one of … silicon nitride (SiN)”) . 9. Regarding Claim 6 , K1, L1 disclose the semiconductor device of claim 1, wherein the first spacer is disposed in the first recess region (see K1 Fig. 2B for a detailed view the first spacer element 131 is in the first recess region – the material is combined with L1) . 10. Regarding Claim 7 , K1, L1 disclose the semiconductor device of claim 6, wherein the first spacer extends between the first bit line structure and a sidewall of the first recess region (see K1 Fig. 2B for a detailed view) . 11. Regarding Claim 8 , K1, L1 disclose the semiconductor device of claim 1, further comprising: a second recess region (see K1 “Labeled Fig. 1B” above, labeled element “Second Recess Region” of element 153) in the substrate and adjacent to the first recess region. 12. Regarding Claim 9 , K1, L1 disclose the semiconductor device of claim 8, further comprising: a storage node contact (see K1 element 153 in labeled element “Second Recess Region”, see [0031] “contact conductive pad 153”; also see electrical connection above through element CPS to the data storage pattern element DSP) in the second recess region. 13. Regarding Claim 10 , K1, L1 disclose the semiconductor device of claim 9, wherein the first spacer contacts the storage node contact (see K1 Fig. 2B for a detailed view element 131 is in contact with element 153 – the material is combined with L1) . 14. Regarding Claim 11 , K1, L1 disclose the semiconductor device of claim 9, wherein the storage node contact contacts a second doped region in the substrate (see K1 element 1b below the labeled element “Second Recess Region”, see [0025] “second impurity region 1b”) . 15. Regarding Claim 12 , K1, L1 disclose the semiconductor device of claim 9, wherein a bottom surface of the first recess region is lower than the storage node contact with respect to the substrate (see K1 “Labeled Fig. 1B” above) . 16. Regarding Claim 13 , K1, L1 disclose the semiconductor device of claim 1, further comprising (see K1 “Labeled Fig. 1B” above) : a second bit line structure (element BLS over element 110) disposed over the substrate, wherein the first spacer extends between the first bit line structure and the second bit line structure (see “Labeled Fig. 1B above”) . 17. Regarding Claim 14 , K1, L1 disclose the semiconductor device of claim 13, wherein the second bit line structure is spaced apart from the substrate by an interlayer (see K1 element 110, see [0032] “insulating interlayer 110”) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL PARK/Examiner, Art Unit 2818 Application/Control Number: 18/640,236 Page 2 Art Unit: 2818
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