DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/23/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 3 of U.S. Patent No. 10,784,855. Although the claims at issue are not identical, they are not patentably distinct from each other for the following reasons:
Regarding claim 2 of the pending application, US Patent ‘855 teaches a method comprising:
controlling a transistor (refer to N-type MOSFET) to set the transistor to be in either a first state or a second state (refer to ON or OFF state), wherein the transistor has a body (refer to body of the MOSFET) (see col. 44, line 65 to col. 45, lines 1-4); and
electrically biasing the body of the transistor with a bias signal during at least a portion of a duration when the transistor is in the second state to control accumulated charge in the body of the transistor (see claim 1, col. 45, lines 3-8 and claim 3).
Claims 2-4,6-15,17-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,967,948. Although the claims at issue are not identical, they are not patentably distinct from each other for the following reasons:
Regarding claim 2 of the pending application, US Patent ‘948 teaches a method comprising:
controlling a transistor (refer to first transistor) to set the transistor to be in either a first state or a second state, wherein the transistor has a body (refer to body of the MOSFET) (see col. 44, lines 41-45); and
electrically biasing the body of the transistor with a bias signal during at least a portion of a duration when the transistor is in the second state to control accumulated charge in the body of the transistor (see claim 1, col. 44, lines 46-49).
Regarding claim 3 of the pending application, US Patent ‘948 discloses the similar features in claim 4.
Regarding claim 4 of the pending application, US Patent ‘948 discloses the similar features in claim 5.
Regarding claim 6 of the pending application, US Patent ‘948 discloses the similar features in claim 3.
Regarding claim 7 of the pending application, US Patent ‘948 discloses the similar features in claim 7.
Regarding claim 8 of the pending application, US Patent ‘948 discloses the similar features in claim 8.
Regarding claim 9 of the pending application, US Patent ‘948 discloses the similar features in claim 11.
Regarding claim 10 of the pending application, US Patent ‘948 discloses the similar features in claim 12.
Regarding claim 12 of the pending application, US Patent ‘948 discloses the similar features in claim 5.
Regarding claim 13 of the pending application, US Patent ‘948 discloses the similar features in claim 17.
Regarding claim 14 of the pending application, US Patent ‘948 discloses the similar features in claim 18.
Regarding claim 15 of the pending application, US Patent ‘948 discloses the similar features in claim 20.
Regarding claim 17 of the pending application, US Patent ‘948 discloses the similar features in claim 12.
Regarding claim 18 of the pending application, US Patent ‘948 discloses the similar features in claim 16.
Regarding claim 19 of the pending application, US Patent ‘948 discloses the similar features in claim 18.
Regarding claim 20 of the pending application, US Patent ‘948 discloses the similar features in claim 11.
Regarding claim 21 of the pending application, US Patent ‘948 discloses the similar features in claim 19.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
Claims 2, 10 and 17 are rejected under pre-AIA 35 U.S.C. 102(a) as being anticipated by Mori (US 2005/0194633).
Regarding claim 2, Mori teaches a method see figs. 5A and 5B comprising:
controlling a transistor (102) to set the transistor to be in either a first state or a second state (refer to writing and erasing state as shown in figs. 5A and 5B), wherein the transistor has a body (100); and
electrically biasing the body of the transistor (refer to 100) with a bias signal (refer to Vb) during at least a portion of a duration when the transistor is in the second state to control accumulated charge in the body of the transistor (see fig. 5B and par. 18).
Regard claim 10, Mori teaches an apparatus in fig. 5A and 5B comprising:
a control circuit (refer to built-in voltage generation circuit as mentioned in par. 8) configured to generate one or more switch control signals (refer to Vg positive or Vg negative); and
a transistor (102) configured to be in either a first state or a second state (refer to writing state or erasing state) based on the one or more switch controls signals (refer to Vg positive or Vg negative), wherein the transistor has a body (100), and wherein the body of the transistor is configured to receive a bias signal during at least a portion of a duration when the transistor is in the second state to control accumulated charge in the body of the transistor (see fig. 5B and par. 18).
Regarding claim 17, Mori teaches an apparatus in figs. 5A-B comprising: means for controlling a transistor to set the transistor to be in either a first state or a second state (refer to applying Vg positive or Vg negative to set gate 102 to be in writing or erasing state), wherein the transistor has a body (100); and
means for electrically biasing the body of the transistor (refer to 100) with a bias signal (refer to Vb) during at least a portion of a duration when the transistor is in the second state to control accumulated charge in the body of the transistor (see par. 18 and fig. 5B).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “…the connecting comprises connecting the first port to the second port when the transistor and one or more additional transistors serially connected to the transistor are in the on state” in combined other limitations of claim 5.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “one or more additional transistors serially connected to the second transistor, wherein the second transistor and the one or more additional transistors are collectively configured to: not shunt the first port to the ground port via the second transistor and the one or more additional transistors during at least a portion of a duration when the first transistor is in the first state; and shunt the first port to the ground port via the second transistor and the one or more additional transistors during at least a portion of a duration when the first transistor is in the second state.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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