DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-13, in the reply filed on 08-10-2026 is acknowledged. New claims 21-27 are drawn to Group I. The election was made without traverse.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koichiro Okamoto (US 20150262864 A1) Hereinafter referred to as “Moto”
Regarding Claim 1 Moto Teaches
A method for manufacturing a semiconductor device (Fig 8 and 12), comprising:
forming a hard mask layer (107 Para [0091]) on a semiconductor substrate (101), the hard mask layer including a first hard mask material (Para [0091] teaches SiCN);
forming a memory structure (121, 122, and 123) on the hard mask layer (107);
forming a lower hard mask (125) on the memory structure, the lower hard mask including a second hard mask material (Para[0104] teaches SiCN) which has an etching rate the same as an etching rating of the first hard mask material (the same material will always have the same etching rate) with respect to a first etchant (Para [0125] teaches CF4Ar gas is added );
forming an upper hard mask(126) on the lower hard mask opposite to the memory structure (Fig 15(b)), the upper hard mask including a third hard mask material (Para[0104] teaches SiO2) which has an etching rate different from an etching rate of the second hard mask material (Para[0123]-[0125]) with a second etchant different (Para [0124] teaches the etchant of oxygen plasma) from the first etchant;
forming an interlayer (108) dielectric (Para [0081] teaches 108 is silicon oxide) layer on the hard mask layer (107) to cover the memory structure, the lower hard mask, and the upper hard mask (Fig 18);
forming a first via opening (Fig 21 element 111) and a second via opening (Fig 7 ) using the first etchant and the second etchant (Para [0090]-[0091] and [0123]-[0125] teach two etchants to form each opening) , the first via opening penetrating (Fig 21) the interlayer dielectric layer(108), the upper hard mask(126), and the lower hard mask(125) to expose the memory structure, the second via opening penetrating (Fig 7) the interlayer dielectric layer(108) and the hard mask layer(107); and
forming a first contact via (Fig 12 element 119) and a second contact via (Fig 8 element 119) in the first via opening and the second via opening, respectively, the first contact via being connected to the memory structure (Fig 12).
Regarding Claim 2 Moto teaches
The method according to claim 1,
wherein the lower hard mask (125) has a thickness (Para [0117] teaches 125 having a thickness of 30nm) which is equal to a thickness (Para [0108] teaches 107 having a thickness of 30nm) of the hard mask layer (107).
Regarding Claim 3 Moto teaches
The method according to claim 1,
wherein the third hard mask material (Para [0104] teaches SiO2 for the layer 126) has a dielectric constant value which is different (they are different) from a dielectric constant value of the second hard mask material (Para [0104] teaches SiCN for layer 125).
Regarding Claim 4 Moto teaches
The method according to claim 1,
wherein the second hard mask material (Para [0104] teaches SiCN for layer 125) is the same as the first hard mask material (Para [0091] teaches SiCN for layer 107).
Regarding Claim 5 Moto teaches
The method according to claim 4,
wherein each of the first hard mask material and the second hard mask material (Para [0091] and [0104] teaches SiCN) includes silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbon nitride, or combinations thereof.
Regarding Claim 6 Moto teaches
The method according to claim 1,
wherein the third hard mask material (Para [0104] teaches SiO2 for the layer 126) is different from the second hard mask material (Para [0104] teaches SiCN for layer 125).
Regarding Claim 21 Moto teaches
A method for manufacturing a semiconductor device (Fig 8 and 12), comprising:
forming a hard mask layer (107 Para [0091]) on an interconnect layer (the layer that includes interconnect 106) including a conductive interconnect (106), the hard mask layer (107) including a first hard mask material (Para [0091] teaches SiCN for layer 107) and being formed with an opening (Fig 14(b)) to expose the conductive interconnect (106);
forming a memory structure (121, 122, 123) on the hard mask layer (107), the memory structure being formed to include a barrier (121) extending through the opening and connected to the conductive interconnect;
forming a lower hard mask(125) on the memory structure, the lower hard mask including a second hard mask material (Para[0104] teaches SiCN) which has an etching rate the same as an etching rating of the first hard mask material (the same material should always have the same etching rate) with respect to a first etchant (Para [0125] teaches CF4Ar gas is added );
forming an upper hard mask (126) on the lower hard mask opposite to the memory structure (Fig 15(b)), the upper hard mask including a third hard mask material (Para[0104] teaches SiO2) which has an etching rate different from an etching rate of the second hard mask material (Para[0123]-[0125]) with a second etchant (Para [0124] teaches the etchant of oxygen plasma) different from the first etchant;
forming an interlayer (108) dielectric (Para [0081] teaches 108 is silicon oxide) layer on the hard mask layer to cover the memory structure, the lower hard mask, and the upper hard mask (Fig 18);
forming a first via opening (Fig 21 element 111) and a second via opening (Fig 7 ) using the first etchant and the second etchant (Para [0090]-[0091] and [0123]-[0125] teach two etchants to form each opening), the first via opening penetrating (Fig 21) the interlayer dielectric layer(108), the upper hard mask(126), and the lower hard mask (125)to expose the memory structure, the second via opening penetrating (Fig 7) the interlayer dielectric layer(108) and the hard mask layer(107); and
forming a first contact via (Fig 12 element 119) and a second contact via (Fig 8 element 119) in the first via opening and the second via opening, respectively, the first contact via being connected to the memory structure. (Fig 12)
Regarding Claim 22 Moto teaches
The method according to claim 21,
wherein the barrier is formed to include: a layer portion which is formed on the hard mask layer; and an insert portion which is formed integrally with the layer portion, and which is inserted into the opening and is connected to the conductive interconnect. (Fig 15(a) and 16(b))
Regarding Claim 23 Moto teaches
The method according to claim 21,
wherein the memory structure is formed to further include a bottom electrode (122) disposed on the barrier (121) opposite to the conductive interconnect, the bottom electrode and the barrier includes different materials.(Para [0116] teaches 121 of material (Ta, Ni, Ti, Zr, Hf, Si, Al, Fe, V, Mn, Co and W, an SiOCH film, a chalcogenide film ) which is different from the material of 122 (Ru) also taught in Para[0116])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moto as applied to claim 6 or and 21 above respectively.
Regarding Claim 7 Moto teaches
The method according to claim 6, further comprising,
before formation of the interlayer dielectric layer (108),
forming a conformal dielectric layer (127 Fig 17 Para [0105]) to cover the memory structure, the lower hard mask, and the upper hard mask, so that the first via opening (Fig 24). and the second via opening further penetrating the conformal dielectric layer
Moto does not show forming layer 127 when they make the second via. However they do teach that the layer 127 protects the device due to its water resistive properties and its oxygen desorption immunity.(Para [0132]) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Moto such that the conformal Dielectric layer is extended over the portion of the device with the second via, because the modification allows improved water-resistance and oxygen desorption immunity. (Para [0132])
Regarding Claim 26 Moto teaches
The method according to claim 21,
further comprising, before formation of the interlayer dielectric layer (108),
forming a conformal dielectric layer (127 Fig 17 Para [0105]) to cover the memory structure, the lower hard mask, and the upper hard mask, so that the first via opening (Fig 24) and the second via opening further penetrating the conformal dielectric layer.
Moto does not show forming layer 127 when they make the second via. However they do teach that the layer 127 protects the device due to its water resistive properties and its oxygen desorption immunity.(Para [0132]) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Moto such that the conformal Dielectric layer is extended over the portion of the device with the second via, because the modification allows improved water-resistance and oxygen desorption immunity. (Para [0132])
Claim(s) 8-9, 25 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moto as applied to claim 7 and 21 above respectively, and further in view of Stephen Gates (US 20050276930 A1) hereinafter referred to as “Gates”
Regarding Claim 8 Moto teaches
The method according to claim 7,
wherein the conformal dielectric layer (127) includes a dielectric material ([0131] teaches the material could be SiCN)
and a third hard mask material (Para [0104] teaches SiO2 for the layer 126).
Moto is not relied upon to teach
wherein the conformal dielectric layer includes a dielectric material which is the same as the third hard mask material
Gates teaches that these dielectric materials that are used as capping layers or mask layers are interchangeable and obvious variants (Para [0029] [0081]) and are therefore relied upon to teach
wherein the conformal dielectric layer includes a dielectric material (Para [0029] teaches silicon oxide) which is the same as the third hard mask material
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Moto such that the conformal dielectric layer is silicon oxide as to match the third hard mask material, as described in Gates because the modification is simple substitution of one known material for another with a known function in the art. (Gates Para [0029][0081])
Regarding Claim 9 Moto in view of Gates teaches
The method according to claim 8,
wherein each of the dielectric material and the third hard mask material includes silicon nitride, silicon oxide (Gates Para [0029] [0081]), tetraethyl orthosilicate, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbon nitride, or combinations thereof.
Regarding Claim 25 Moto teaches
The method according to claim 21,
Moto is not relied upon to teach
wherein the hard mask layer and the lower hard mask include silicon carbide.
Gates teaches that these dielectric materials that are used as capping layers or mask layers are interchangeable and obvious variants (Para [0029] [0081]) and are therefore relied upon to teach
wherein the hard mask layer and the lower hard mask include silicon carbide.
(Para [0029] teaches silicon Carbide as a variant)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Moto such that the hard mask layer and the lower hard mask include silicon carbide, as described in Gates because the modification is simple substitution of one known material for another with a known function in the art. (Gates Para [0029][0081])
Regarding Claim 27 Moto teaches
The method according to claim 26,
wherein the upper hard mask (Para [0104] teaches SiO2)
Gates teaches that these dielectric materials that are used as capping layers or mask layers are interchangeable and obvious variants (Para [0029] [0081]) and are therefore relied upon to teach
the conformal dielectric layer include a same material which includes silicon oxide (Para [0029]), tetraethyl orthosilicate, or a combination thereof.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Moto such that the conformal dielectric layer includes silicon oxide, as described in Gates because the modification is simple substitution of one known material for another with a known function in the art. (Gates Para [0029] [0081])
Claim(s) 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moto, and further in view of Hai-Dang Trinh (US 11309491 B2) hereinafter referred to as “Tri”
Regarding Claim 10 Moto teaches
A method for manufacturing a semiconductor device (Fig 8 and 12), comprising:
forming a first hard mask layer (107 Para [0091]) on a semiconductor substrate (101), the first hard mask layer including a first hard mask material (Para [0091] teaches SiCN);
sequentially forming (a stack (121, 122, 123) and then forming), a second hard mask layer (125), and a third hard mask layer (126)on the first hard mask layer, the second hard mask layer including a second hard mask material (Para[0104] teaches SiCN for layer 125) which is the same as the first hard mask material, the third hard mask layer including a third hard mask material (Para[0104] teaches SiO2) which is different from the second hard mask material;
patterning (Fig 16(b)) the third hard mask layer, the second hard mask layer (and a stack (121, 122, 123)), to form a memory structure on the first hard mask layer, a lower hard mask (125 after patterning)on the memory structure, and an upper hard mask(126 after patterning) on the lower hard mask opposite to the memory structure, the lower hard mask including the second hard mask material, the upper hard mask including the third hard mask material;
forming an interlayer (108) dielectric (Para [0081] teaches 108 is silicon oxide) layer on the first hard mask layer (107) to cover the memory structure, the lower hard mask, and the upper hard mask (Fig 18);
forming a first via opening (Fig 21 element 111) and a second via opening (Fig 7), the first via opening penetrating (Fig 21) the interlayer dielectric layer (108), the upper hard mask (126), and the lower hard mask (125) to expose the memory structure, the second via opening penetrating the interlayer dielectric layer and the first hard mask layer; and
forming a first contact via (Fig 12 element 119) and a second contact via (Fig 8 element 119) in the first via opening and the second via opening, respectively, the first contact via being connected to the memory structure (Fig 12).
Moto teaches a stack but does not teach
sequentially forming a barrier material layer, a bottom electrode material layer, a high-k dielectric material layer, a top electrode material layer, a capping material layer
Tri teaches a similar memory structure stack that has the layers
sequentially forming a barrier material layer (120), a bottom electrode material layer (124), a high-k dielectric material layer (128, 130 and 132 Col 5 lines 39-57), a top electrode material layer (134), a capping material layer (508)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Moto and replace the stack with a different memory structure stack such that the device contains the layers of a barrier material layer , a bottom electrode material layer, a high-k dielectric material layer, a top electrode material layer, and a capping material layer, as described in Tri because the modification is a simple substation of memory structure stacks that complete the same function that is known in the art. (Tri memory cell 122 Col 5 lines 39-57)
Regarding Claim 11 Moto in view of Tri teaches
The method according to claim 10,
Moto further teaches
wherein the second hard mask layer (125) has a thickness (Para [0117] teaches 125 having a thickness of 30nm) which is equal to a thickness (Para [0108] teaches 107 having a thickness of 30nm) of the first hard mask layer (107).
Regarding Claim 12 Moto in view of Tri teaches
The method according to claim 10,
Moto further teaches
wherein the third hard mask layer (126) has a thickness (Para [0117] teaches 126 having a thickness of 100nm) which is greater than a thickness (Para [0117] teaches 125 having a thickness of 30nm) of the second hard mask layer (125).
Regarding Claim 13 Moto in view of Tri teaches
The method according to claim 10,
wherein patterning (Moto Fig16(b)) of the third hard mask layer, the second hard mask layer (and the memory stack taught in Tri), the capping material layer, the top electrode material layer, the high-k dielectric material layer, the bottom electrode material layer, and the barrier material layer includes:
forming a patterned photoresist layer (Moto Para [0123] teaches lithography) on the third hard mask layer (126)
performing an etching process through the patterned photoresist layer to pattern the third hard mask layer while removing the patterned photoresist layer, so as to permit the third hard mask layer to include a bottom portion (due to the nature of dry etching at some point when you are removing the material of 126 there will be a bottom portion that is not fully etched away yet on the edges of the pattern and upper portions under the pattern that have yet to be fully etched that will sit above the bottom portions) and a plurality of upper portions protruding in an upward direction away from the semiconductor substrate; and
continuously performing the etching process through a patterned hard mask formed by the plurality of upper portions of the third hard mask layer (Para [0123]) until the first hard mask layer (107) is exposed. (Fig 16(b)).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moto as applied to claim 21 above, and further in view of Tri in view of Kam-Leung Lee (US 20200020542 A1) hereinafter referred to as “Lee”
Regarding Claim 24 Moto teaches
The method according to claim 23,
Moto is not relied upon to teach
wherein the memory structure is formed to further include a high-k dielectric element disposed on the bottom electrode opposite to the barrier, a top electrode disposed on the high-k dielectric element opposite to the bottom electrode, and a cap disposed on the top electrode opposite to the high-k dielectric element, the cap including cobalt.
Tri teaches a similar memory structure that does teach
wherein the memory structure (Fig 5) is formed to further include a high-k dielectric element (128, 130 and 132 Col 5 lines 39-57) disposed on the bottom electrode(124) opposite to the barrier (120), a top electrode(134) disposed on the high-k dielectric element opposite to the bottom electrode, and a cap (508) disposed on the top electrode opposite to the high-k dielectric element
Moto in view of Tri is not relied upon to teach
the cap including cobalt.
Lee teaches a capping layer in a memory device and therefore is relied upon to teach
the cap (18) including cobalt. (Para [0031])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Moto in view of Tri such that the cap includes cobalt, as described in Lee because the modification is a simple substitution of known capping materials with a known function. (Lee Para [0031])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Saito; Yukishige (US-20120286231-A1), Tada; Munehiro (US-8946672-B2), Chang; Chih-Yang (US-20150090949-A1), Sung; Fu-Ting (US-20160268505-A1) TRINH; Hai-Dang (US-20190165266-A1), Ando; Takashi (US-20200220078-A1), Kong; Dexin (US-20210265566-A1), CHIU; Chieh-Fei (US-20220102428-A1), CHEN; Hsia-Wei (US-20220216106-A1), Hsu; Chern-Yow (US-11495743-B2), Chen; Hsia-Wei (US-20230284540-A1), Liu; Watson (US-20250366380-A), Chuang; Harry-Haklay (US-20260101679-A1), LIN; Yen-Liang (US-20260165040-A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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