DETAILED ACTION
This action is responsive to application No. 18/641,017 filed on 04/19/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, species 7 (Claims 1-6, 8-9) in the reply filed on 07/20/2026 is acknowledged. Applicant added new claims 21-30.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Objections
Claim 23 objected to because of the following informalities:
Claim 23 states that “the thermal dissipation layer includes depositing diamond-like carbon.” Because the claimed semiconductor device is an apparatus (device), it may be unclear how a completed layer “includes depositing” a material. A clearer limitation would be “wherein the thermal dissipation layer comprises deposited diamond-like carbon” or simply “comprises diamond-like carbon.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 25-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 25 recites “the MLI” in line 5. However, neither “an MLI” nor “a multilayer interconnect structure” is previously introduced in the claim. Although claim 25 previously recites “a first metal layer and an overlying second metal layer over the first transistor, wherein a via extends between the first metal layer and the overlying second metal layer,” it is unclear whether “the MLI” is intended to collectively refer to the previously recited first metal layer, second metal layer, and via, or whether “the MLI” refers to a separate, additional multilayer interconnect structure that has not otherwise been recited.
Claim 25 subsequently recites “a second diamond-like carbon layer over the MLI.” This recitation creates further uncertainty because it is unclear whether this second reference to “the MLI” refers to the same unidentified MLI associated with the first diamond-like carbon layer, to the previously recited third and fourth metal layers and another via, or to another separate multilayer interconnect structure.
Accordingly, the lack of antecedent basis for “the MLI,” together with the multiple reasonable interpretations of that term, renders the scope of claim 25 unclear. Specifically, it cannot be determined whether claim 25 requires one MLI shared by the first and second diamond-like carbon layers, respective first and second MLIs associated with the respective first and second transistor devices, or one or more additional MLIs separate from the expressly recited metal layers and vias. Therefore, the metes and bounds of claim 25 cannot be determined with reasonable clarity.
Claim 5 recites:
“wherein the surface with the plurality of peaks and valleys has an RMS value of hundreds of nanometers to micrometers in peak to valley height.”
Although “the surface with the plurality of peaks and valleys” has antecedent basis in claim 1 and is understood to refer to the recited surface of the thermal-dissipation layer, the remainder of the limitation does not clearly define the required surface characteristic.
In particular, it is unclear whether claim 5 requires:
1. An RMS surface-roughness value in the hundreds-of-nanometers-to-micrometers range;
2. A peak-to-valley height in that range; or
3. Both an RMS surface-roughness value and a peak-to-valley height satisfying that range.
RMS surface roughness and peak-to-valley height are different measurements of surface topography. Therefore, the phrase “an RMS value … in peak to valley height” creates uncertainty regarding which measurement is being claimed.
Additionally, the phrase “hundreds of nanometers to micrometers” does not provide reasonably clear numerical boundaries. It is unclear what value constitutes the lower boundary of “hundreds of nanometers” and what value constitutes the upper boundary of “micrometers.”
Accordingly, one of ordinary skill in the art would not be able to determine the metes and bounds of claim 5. Claim 5 is therefore indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2014/0225258 to Chiu et al. (Chiu) in view of US Pat # 6,051,473 to Ishida et al. (Ishida) and further in view of US Pub # 2007/0269604 to Francis et al. (Francis).
Regarding independent claim 1, Chiu discloses an integrated circuit (IC) structure (Fig. 4), comprising:
a transistor device (¶0033) formed on a substrate (56), the transistor device having source/drain (S/D) regions and a gate structure. Chiu does not expressly identify the transistor within die 54 as a field-effect transistor having source/drain regions and a gate structure. Ishida teaches a conventional metal-oxide-semiconductor field-effect transistor (MOSFET) formed on a silicon substrate 110. As illustrated in Figure 1, the MOSFET includes deep source/drain regions 150 and source/drain extension regions 130 formed within substrate 110. Ishida further teaches a gate 120 and an insulating gate-oxide layer 115 formed over substrate 110. Gate 120 and gate-oxide layer 115 collectively correspond to the claimed gate structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to implement the transistors within Chiu’s die 54 as conventional MOSFETs having the source/drain regions and gate structure taught by Ishida. Ishida identifies a MOSFET as a typical semiconductor device and a primary building block in the semiconductor industry (col. 1, lines 15-17). Therefore, using Ishida’s conventional MOSFET structure for Chiu’s expressly disclosed transistors would have amounted to using a known transistor structure according to its established function, producing the predictable result of providing transistor devices capable of performing the switching and circuit operations of Chiu’s integrated-circuit die 54;
Chiu further discloses a multi-layer interconnect (MLI) structure (Fig. 4: 30) over the transistor device (54), wherein the MLI (30) includes metal lines (36) and metal vias (40) embedded in an intermetal dielectric (IMD) layer (38), see (¶0020);
a bonding layer (22) over the multi-layer interconnect (MLI) structure (30).
Chiu does not expressly disclose a thermal dissipation layer having a surface with a plurality of peaks and valleys disposed over at least a portion of the MLI structure; and
a bonding layer over the thermal dissipation layer and covering the plurality of peaks and valleys.
Francis discloses diamond heat-spreading layers for removing and laterally spreading heat generated by electronic and integrated-circuit devices. In the embodiment of Figure 6(a), Francis discloses CVD diamond film 601 serving as a thermal-dissipation or heat-spreading layer. Diamond film 601 has a rough top surface 604. Francis explains that surface 604 has roughness significantly greater than the surface of substrate 603 and may have roughness as large as approximately 10% of the total thickness of diamond film 601 (paragraph 44). The repeated protrusions and depressions of rough surface 604 illustrated in Figure 6(a) correspond to the claimed plurality of peaks and valleys.
Francis further discloses depositing a surface-conforming bonding agent over diamond film 601 to form bonding layer 611 (Figure 6(a) and paragraph 45). Because bonding layer 611 is deposited over and conforms to rough surface 604, bonding layer 611 covers the peaks and valleys of rough surface 604.
It would have been obvious to one of ordinary skill in the art before the effective filing date to provide the semiconductor structure of Chiu with the diamond heat-spreading structure of Francis over at least a non-contact portion of interconnecting structure 30. In making the combination, the skilled artisan would have positioned preformed diamond film 601 over at least a portion of interconnecting structure 30 and provided surface-conforming bonding layer 611 over rough surface 604, while leaving the electrical contact areas available for electrical connection.
Chiu recognizes heat dissipation as a relevant consideration and explains that its interconnecting vias may improve heat dissipation within interconnecting structure 30. Francis explains that diamond heat-spreading layers efficiently carry heat away from localized electronic heat sources, that diamond has exceptionally high thermal conductivity, and that positioning the diamond heat spreader close to the heat source improves heat spreading (¶0006). A person of ordinary skill therefore would have used the diamond heat-spreading and bonding arrangement of Francis with Chiu’s integrated-circuit structure to improve lateral heat spreading (¶0006), reduce localized device temperature (¶0009), and provide effective thermal contact with an adjacent supporting structure (¶0006). The combination would have involved the predictable use of Francis’s known heat-spreading structure for its established thermal-dissipation function, with a reasonable expectation of success.
Regarding claim 4, Chiu as previously modified teaches an integrated-circuit structure including a semiconductor die 54 and a multilayer interconnect structure 30 having multiple metal layers M1–Mn, metal lines 36, vias 40, and intermetal dielectric layers 38 (see Chiu, Figures 2A–2H and Figure 4 and the corresponding description).
However, Chiu does not teach that a thermal-dissipation layer disposed over the multilayer interconnect structure is formed from a diamond-like material. In particular, Chiu’s layer 32 is described as an etch-stop layer and is not expressly identified as a diamond-like thermal-dissipation layer.
Francis teaches using diamond-based materials as thermal-dissipation or heat-spreading layers for electronic and integrated-circuit structures. Francis specifically teaches depositing a CVD diamond film 601 that functions as a heat-spreading layer. Francis also states that its disclosure relates to diamond films, diamond-like carbon, and synthetic diamond used in heat sinks (see Francis, Figure 6(a), ¶0044).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiu’s integrated-circuit structure by forming Francis’s diamond or diamond-like thermal-dissipation layer over at least a portion of Chiu’s multilayer interconnect structure.
One of ordinary skill would have been motivated to make this modification because Francis teaches that a diamond or diamond-like layer functions as a heat-spreading layer and improves the removal of heat generated by electronic or integrated-circuit devices. Applying Francis’s known diamond-based thermal-management layer to Chiu’s multilayer interconnect structure would predictably spread heat away from the semiconductor device and interconnect structure, thereby improving thermal management and device reliability.
Regarding claim 5, Chiu as previously modified teaches an integrated-circuit structure including a semiconductor die 54 and a multilayer interconnect structure 30 having multiple metal layers M1–Mn, metal lines 36, vias 40, and intermetal dielectric layers 38 (see Chiu, Figures 2A–2H and Figure 4 and the corresponding description).
However, Chiu does not teach wherein the surface with the plurality of peaks and valleys has an RMS value of hundreds of nanometers to micrometers in peak to valley height.
Francis teaches that a deposited diamond film may have a thickness ranging from approximately 1 micrometer to 1,000 micrometers and that the RMS roughness of the deposited top surface may be as large as approximately 10% of the film thickness. Francis also depicts the rough surface 604 as having peaks and valleys (see Francis, Figure 6(a), ¶0044), and the general description of CVD-diamond-film thickness and surface roughness.
Thus, depending on the selected film thickness, Francis’s disclosed roughness includes values in the hundreds-of-nanometers-to-micrometers range. For example, a film thickness of 10 micrometers with an RMS roughness of approximately 10% produces a roughness of approximately 1 micrometer. Francis’s disclosed range therefore overlaps the claimed range.
It would have been obvious to select the film thickness and corresponding surface roughness from Francis’s disclosed ranges because both are recognized result-effective manufacturing parameters affecting heat spreading, surface contact, and bonding.
Regarding claim 6, Chiu as previously modified teaches the limitations of claim 1 from which this claim depends.
Chiu as previously modified fails to teach wherein the bonding layer is AlN such that one of ordinary skill in the art would be motivated to seek exemplary metals known in the art
Francis expressly identifies aluminum nitride as one of the alternative materials that may be used for bonding layer 611 (see Francis ¶0045; see also claim 32 of Francis) and it would have been obvious to one of ordinary skill in the art at the time of the invention to have selected AlN for the undisclosed metal as mere selection of an art-recognized metal suitable for the intended use of Chiu (MPEP $2144.07).
Regarding claim 8, Chiu as previously modified teaches the limitations of claim 1 from which this claim depends.
Chiu as previously modified fails to teach wherein each of the plurality of peaks and valleys are entirely covered by the bonding layer.
Francis teaches a CVD diamond film 601 that functions as a thermal-dissipation or heat-spreading layer. Francis teaches that the top surface 604 of diamond film 601 is rough and has a plurality of peaks and valleys. Francis further teaches depositing a surface-conforming bonding agent over diamond film 601 to form bonding layer 611. As shown in Figure 6(a), bonding layer 611 is a continuous layer that follows and covers the rough surface 604, thereby entirely covering the peaks and valleys of surface 604 (see Francis, Figure 6(a) and ¶0044-0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiu’s integrated-circuit structure by forming Francis’s diamond thermal-dissipation layer over Chiu’s multilayer interconnect structure and depositing Francis’s surface-conforming bonding layer over the rough diamond surface such that the bonding layer entirely covers each of its peaks and valleys.
One of ordinary skill in the art would have been motivated to make this modification because Francis teaches that the diamond layer spreads heat away from an electronic device and that the surface-conforming bonding layer adheres the diamond layer to a carrier or heat-sink substrate. Completely covering the rough surface, including its peaks and valleys, would provide a continuous bonding interface, improve adhesion between the layers, and facilitate the transfer of heat from the diamond layer to the heat-sink substrate.
Regarding claim 9, Chiu as previously modified teaches the limitations of claim 1 from which this claim depends.
Chiu as previously modified fails to teach the bonding layer includes at least one of AlN, cubic BN (c-BN), BP, A1203, SiN, BeO, or SiO2.
Francis teaches depositing a surface-conforming bonding agent over diamond film 601 to form bonding layer 611. Francis expressly teaches that suitable materials for bonding layer 611 include, among other materials, aluminum nitride, silicon nitride, and silicon oxide (see Francis, Figure 6(a), ¶0045, and claim 32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiu’s integrated-circuit structure by forming Francis’s diamond thermal-dissipation layer over Chiu’s multilayer interconnect structure and forming Francis’s bonding layer, comprising aluminum nitride, silicon nitride, or silicon oxide, over the diamond thermal-dissipation layer.
One of ordinary skill in the art would have been motivated to make this modification because Francis identifies these materials as suitable bonding agents based on their ability to adhere to diamond and a carrier substrate and based on their bonding temperature, operating temperature, and electrical and thermal-conductivity properties. Selecting one of Francis’s expressly disclosed bonding materials would therefore have predictably provided adhesion between the thermal-dissipation layer and an overlying substrate while maintaining suitable thermal and electrical characteristics.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2014/0225258 to Chiu et al. (Chiu) in view of US Pat # 6,051,473 to Ishida et al. (Ishida) in view of US Pub # 2007/0269604 to Francis et al. (Francis) and further in view of US Pat # 6,902,987 to Tong et al. (Tong).
Regarding claim 2, Chiu in view of Francis and Ishida teaches the IC structure of claim 1. Francis further teaches that the diamond film 601 has a rough top surface 604 and that a surface-conforming bonding agent is deposited over the diamond film to form bonding layer 611. Francis teaches that the roughness of surface 604 is significantly greater than that of the underlying smooth substrate surface and may be as large as approximately 10% of the thickness of the diamond film (see Francis, Figure 6(a) and ¶0044-0045).
The combinations of Chiu in view of Francis and Ishida do not expressly state that the exposed first surface of bonding layer 611 has an RMS value less than the RMS value of the rough surface 604 of the thermal-dissipation layer.
Tong teaches forming a bonding layer 32 over an underlying structure and planarizing and smoothing the exposed bonding surface 33 by chemical-mechanical polishing. Tong teaches that surface 33 preferably has a roughness no greater than approximately 3 nm and, more preferably, no greater than approximately 0.1 nm. Tong expressly identifies these roughness values as RMS values (see Tong, Figures 3A–3B and col. 4, lines 58-67 and col. 5, lines 1-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to planarize the exposed surface of Francis’s bonding layer 611 according to Tong. The motivation would have been to provide a smooth and substantially planar bonding surface, thereby improving contact, bonding uniformity, and bonding reliability (see Tong, col. 5, lines 31-40 and col. 9, lines 30-36). Because Francis’s underlying diamond surface 604 is expressly rough and may have an RMS roughness substantially greater than 3 nm, Tong’s polished bonding surface would have an RMS value less than the RMS value of the thermal-dissipation-layer surface (col. 2, lines 43-52).
Regarding claim 3, Chiu in view of Francis and Ishida teaches the IC structure of claim 2, as set forth above. However, the combination of Chiu, Francis, and Ishida does not expressly teach wherein the first surface of the bonding layer has an RMS value of less than 1 nanometer.
Tong teaches forming a bonding layer 32 over an underlying structure and planarizing and smoothing the exposed surface 33 of bonding layer 32, such as by chemical-mechanical polishing. Tong teaches that surface 33 is preferably polished to a roughness of no more than approximately 3 nanometers and, more preferably, no more than approximately 0.1 nanometer (Tong, col. 5, lines 17-30). Tong further expressly explains that these surface-roughness values are root-mean-square, or RMS, values (se Tong, Figures 3A–3B and col. 5, lines 17-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to planarize the exposed surface of previously modified Francis’s bonding layer 611 according to the teachings of Tong. One would have been motivated to do so to provide a smooth and substantially planar bonding surface, thereby improving surface contact, bonding uniformity, and bonding reliability (see Tong, col. 5, lines 31-40 and col. 9, lines 30-36). Because Tong teaches (col. 5, lines 17-30) an RMS roughness as low as approximately 0.1 nanometer, the modified bonding layer would have an RMS value of less than 1 nanometer and less than the RMS value of Francis’s rough diamond surface 604.
Tong further teaches that the RMS roughness of the bonding surface is preferably no greater than approximately 0.1 nm, which is less than 1 nanometer (see Tong, col. 5, lines 16-30).
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2014/0225258 to Chiu et al. (Chiu) in view of US Pub # 2007/0269604 to Francis et al. (Francis).
Regarding independent claim 21, Chiu discloses a semiconductor device, comprising:
a transistor on a semiconductor substrate (Die 54 is a semiconductor device die, and the disclosed transistor is formed as part of the integrated circuitry of the die, see Fig. 4 and ¶0033);
Chiu further discloses multiple metal layers M1 through Mn over the active surface of die 54. Two adjacent metal layers, such as metal layer Mn and the spatially overlying metal layer M3 illustrated in Figure 4, correspond respectively to the claimed first metal layer and overlying second metal layer. Vias 40 extend between and electrically connect adjacent metal layers;
Chiu does not expressly disclose a thermal dissipation layer over the overlying second metal layer, wherein the thermal dissipation layer includes a rough surface exhibiting peaks and valleys, and a bonding layer over the rough surface, wherein the bonding layer covers at least one peak and valley of the rough surface and another substrate over the bonding layer.
Francis teaches a thermal-dissipation and bonding arrangement having these features. Specifically, Francis discloses diamond film 601 for use in a heat sink to conduct and spread heat away from an electronic device (see Francis, ¶0003, 0005-0006). Accordingly, diamond film 601 corresponds to the claimed thermal-dissipation layer.
Francis further teaches that diamond film 601 has a rough top surface 604. Francis expressly states that surface 604 of deposited diamond film 601 has surface roughness and may have significantly greater roughness than surface 602 of substrate 603 (see Francis, Figure 6(a) and ¶0044). A person of ordinary skill in the art would have understood that rough surface 604 necessarily includes raised and recessed surface portions corresponding to the claimed peaks and valleys.
Francis additionally teaches depositing a surface-conforming bonding agent over rough surface 604 of diamond film 601 to form bonding layer 611. Because the bonding agent is surface-conforming, bonding layer 611 conforms to and covers raised and recessed portions of rough surface 604, including at least one peak and at least one valley (see Francis, Figure 6(a), particularly intermediate structure 610, and ¶0045).
Francis also teaches “another substrate over the bonding layer.” Specifically, the claimed another substrate corresponds to heat-sink substrate 621 in the final assembly 620 of Francis’s Figure 6(a). Francis teaches placing the diamond-film structure on heat-sink substrate 621 such that bonding layer 611 is directly adjacent to substrate 621 (see Francis, Figure 6(a), final assembly 620, and ¶0046). Bonding layer 611 is therefore positioned between diamond film 601 and heat-sink substrate 621.
Although Figure 6(a) may depict substrate 621 below bonding layer 611 based on the page orientation, the claimed term “over” describes the relative stacked relationship rather than a gravitational direction. In Francis’s final assembly 620, the disclosed structural sequence is diamond film 601, bonding layer 611, and heat-sink substrate 621. When Francis’s diamond film 601 is disposed over the upper metallization layer of Chiu’s interconnecting structure 30, bonding layer 611 is disposed over diamond film 601, and substrate 621 is correspondingly disposed over bonding layer 611.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiu’s semiconductor device by providing Francis’s diamond film 601 over the upper metallization layer of Chiu’s interconnecting structure 30, providing Francis’s surface-conforming bonding layer 611 over rough surface 604 of diamond film 601, and coupling heat-sink substrate 621 to bonding layer 611.
A person of ordinary skill in the art would have been motivated to make this modification to improve the conduction and spreading of heat away (see Francis, ¶0017 and 0056) from Chiu’s transistor device and multilayer interconnecting structure. Chiu recognizes heat dissipation as a consideration in its semiconductor structure (see Chiu, ¶0023). Francis specifically teaches using diamond films in heat sinks to conduct heat away from electronic devices and further teaches using a surface-conforming bonding layer to attach the rough diamond film to another substrate (see Francis, ¶0003, 0005-0006, and 0044-0046 and 0056).
Regarding claim 22, Chiu teaches a semiconductor device including a semiconductor die 54 and a multilayer interconnect structure 30. The interconnect structure includes multiple metal layers M1-Mn, metal lines 36, and vias 40 extending between adjacent metal layers (see Chiu, Figures 2A-2H and 4 and the corresponding description).
However, Chiu does not teach a bonding layer includes at least one of AlN, cubic BN, BP, Al₂O₃, SiN, BeO, or SiO₂.
Francis teaches a CVD diamond film 601 that functions as a thermal-dissipation or heat-spreading layer. The diamond film has a rough surface 604 exhibiting peaks and valleys. Francis further teaches depositing a surface-conforming bonding agent over rough surface 604 to form bonding layer 611 and placing heat-sink substrate 621 over and directly adjacent bonding layer 611. Francis expressly teaches that suitable bonding materials include aluminum nitride, silicon nitride, and silicon oxide (see Francis, Figure 6(a), ¶0044-0046, and claim 32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiu’s semiconductor device by forming Francis’s rough diamond thermal-dissipation layer over Chiu’s metal interconnect structure, forming Francis’s bonding layer over the rough surface, and bonding an additional substrate to the bonding layer, wherein the bonding layer comprises AlN, SiN, or SiO₂.
One of ordinary skill in the art would have been motivated to make this modification because Francis teaches that the diamond layer spreads heat away from an electronic device (¶0044 and 0056) and that AlN, SiN, and SiO₂ are suitable bonding materials based on their adhesion, bonding temperature, operating temperature, and electrical and thermal properties. Using one of Francis’s expressly disclosed materials would predictably bond the diamond layer to the overlying substrate while maintaining suitable thermal and electrical characteristics.
Regarding claim 23, Chiu teaches a semiconductor device including a semiconductor die 54 and a multilayer interconnect structure 30 having metal layers M1-Mn, metal lines 36, vias 40, and intermetal dielectric layers 38.
However, Chiu does not teach a thermal-dissipation layer includes deposited diamond-like carbon.
Francis teaches depositing a CVD diamond film 601 that functions as a thermal-dissipation or heat-spreading layer. Francis expressly states that its disclosure concerns the chemical-vapor deposition of diamond films, diamond-like carbon, and synthetic diamond for use in heat sinks. Francis also teaches that diamond film 601 is deposited on substrate surface 602 and that a bonding layer 611 is subsequently deposited over rough surface 604 (see Francis, Figure 6(a), and ¶0003 and 0044-0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiu’s semiconductor device by depositing Francis’s diamond-like carbon thermal-dissipation layer over Chiu’s multilayer interconnect structure.
One of ordinary skill in the art would have been motivated to make this modification because Francis teaches that deposited diamond and diamond-like carbon layers provide heat-spreading properties and improve heat removal from electronic and integrated-circuit devices (¶0044, 0056). Applying Francis’s deposited diamond-like carbon layer over Chiu’s metal interconnect structure would predictably improve thermal dissipation and conduct heat away from the semiconductor device and its interconnect structure (¶0006 and 0044).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2014/0225258 to Chiu et al. (Chiu) in view of US Pub # 2007/0269604 to Francis et al. (Francis) and further in view of US Pat # 5,559,367 to Cohen et al. (Cohen).
Regarding claim 24, Chiu teaches a semiconductor device including a semiconductor die 54 and a multilayer interconnect structure 30. The interconnect structure includes multiple successively arranged metal layers M1-Mn and vias 40 extending between adjacent metal layers.
Chiu teaches additional third and fourth metal layers over the first and second metal layers and another via extending between the additional metal layers (see Chiu, Figures 2A-2B and Figure 4 and the corresponding description).
However, Chiu does not teach a diamond-like carbon material surrounding the third metal layer, the fourth metal layer, and the via extending between those metal layers.
Francis teaches depositing a diamond-based thermal-dissipation layer over an underlying structure, forming bonding layer 611 over rough surface 604, and bonding heat-sink substrate 621 to bonding layer 611. Francis further identifies diamond-like carbon as a material useful in its disclosed heat-spreading structures.
Cohen teaches using diamond-like carbon as an interlevel and intralevel dielectric material in a multilevel semiconductor interconnect structure. In Figure 3, Cohen teaches first and second metal interconnect levels 42 and 43, an interlevel metal-filled via 45 extending between the metal levels, and diamond-like carbon material 46 surrounding and electrically insulating the metal interconnect levels and via (col. 6, lines 5-21). Cohen’s Figure 4 similarly teaches copper interconnects and studs 54 surrounded by diamond-like carbon dielectric layers 58 (col. 9, lines 4-28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Chiu-Francis semiconductor structure by employing Cohen’s diamond-like carbon material around Chiu’s third and fourth metal layers and the via extending between those metal layers.
One of ordinary skill in the art would have been motivated to make this modification because Cohen teaches that diamond-like carbon functions as an interlevel dielectric that electrically insulates adjacent metal conductors and possesses a relatively low dielectric constant (col. 9, lines 4-10). Cohen further teaches that using diamond-like carbon around multilevel interconnects reduces parasitic capacitance and crosstalk (col. 9, lines 38-46). Employing Cohen’s DLC material around Chiu’s metal layers and intervening via would therefore have predictably provided electrical insulation while improving the electrical performance of the multilevel interconnect structure.
Claims 25 and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2014/0225258 to Chiu et al. (Chiu) in view of US Pub # 2007/0269604 to Francis et al. (Francis) and further in view of US Pub # 2015/0349004 to Qian et al. (Qian).
Regarding independent claim 25, Chiu discloses a semiconductor structure comprising:
a first transistor device on a first semiconductor substrate (as evidenced by semiconductor die 54 illustrated in Figure 4. Chiu discloses that die 54 is a device die comprising integrated-circuit devices, including transistors, see ¶0030. The semiconductor material of die 54 on or in which the transistors are formed corresponds to the claimed first semiconductor substrate),
Chiu further teaches a first metal layer (Fig. 4: M1) and an overlying second metal layer (Fig. 4: M2) over the first transistor (54), wherein a via (40) extends between the first metal layer (M1) and the overlying second metal layer (M2);
Chiu does not expressly teach a first diamond-like carbon layer over the multilayer interconnect structure, wherein the first diamond-like carbon layer having a surface with an RMS of the surface of at least hundred nanometers, and a first bonding layer over the diamond-like carbon layer.
Francis teaches diamond-based heat-spreading layers for conducting heat away from electronic devices and integrated circuits. Francis explains that the purpose of a heat-spreading layer is to carry heat away from a relatively small heat source and distribute the heat over a larger area where it may be more efficiently removed (see Francis ¶0005-0006). Francis further expressly states that its invention relates to chemical vapor deposition of diamond films, diamond-like carbon, and synthetic diamond, and the use of these materials in heat sinks (see Francis, ¶0003).
Francis’s Figure 6A and ¶0044 illustrate a diamond heat-spreading film 601 having a rough top surface 604. Francis explains that top surface 604 has a roughness significantly greater than the roughness of underlying substrate surface 602 and that the roughness of top surface 604 is large as 10% of the total thickness of diamond film 601. Francis also explains that deposited diamond films may have an RMS surface roughness as high as 10% of the thickness of the deposited film (see Francis, ¶0018). Francis further discloses that its diamond film generally has a thickness between 1 and 1,000 micrometers and that the roughness of its top surface is between 1 and 10 percent of the film growth thickness (see Francis, ¶0055).
Accordingly, Francis teaches a roughness range that encompasses an RMS roughness of at least hundred nanometers. For example, an RMS roughness equal to 10% of a film thickness of 1 micrometer is 0.1 micrometer, or 100 nanometers. Moreover, larger film thicknesses within Francis’s disclosed range produce disclosed roughness values substantially greater than 100 nanometers. Therefore, the claimed lower limit of at least 100 nanometers falls within the roughness values taught or suggested by Francis.
Francis also teaches “a first bonding layer over the first diamond-like carbon layer.” Specifically, (Figure 6A and ¶0045) disclose depositing a surface-conforming bonding agent over rough top surface 604 of diamond film 601, thereby forming bonding layer 611. Because bonding layer 611 is surface conforming, bonding layer 611 follows and covers the rough features of surface 604.
Francis additionally teaches positioning another substrate over the bonding layer. Figure (6A and ¶0046) disclose turning the structure over and placing it on heat-sink substrate 621 so that bonding layer 611 is directly adjacent to substrate 621. Accordingly, substrate 621 corresponds to a substrate positioned over the first bonding layer when the structure is viewed in the claimed orientation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiu by forming a diamond-based heat-spreading layer, such as the diamond-like carbon material identified by Francis, over interconnecting structure 30, and forming a surface-conforming bonding layer over the rough surface of that heat-spreading layer, as taught by Francis.
A person of ordinary skill would have been motivated to make this modification because Chiu expressly recognizes that heat dissipation within interconnecting structure 30 is desirable, while Francis teaches that diamond and diamond-like-carbon heat-spreading layers efficiently carry heat away from localized heat-generating electronic devices and distribute that heat over a larger area (see Chiu, ¶0023), regarding the use of vias 40 to improve heat dissipation, and Francis, ¶0005-0006 and 0009). The modification would have predictably improved the dissipation of heat generated by the transistor devices of die 54 (¶0023).
It also would have been obvious to select a disclosed film thickness and surface roughness from Francis’s disclosed ranges that produces an RMS surface roughness of at least 100 nanometers. The claimed RMS value falls within Francis’s disclosed roughness range, and selection of a value within an expressly disclosed range would have been within the ordinary skill in the art absent evidence that the claimed value produces an unexpected result.
The combination of Chiu and Francis, however, does not expressly teach “a second semiconductor substrate over the first bonding layer, a second transistor device on the second semiconductor substrate, a third metal layer and an overlying fourth metal layer over the second transistor, wherein another via extends between the third metal layer and the overlying fourth metal layer, a second diamond-like carbon layer over the MLI, wherein the second diamond-like carbon layer has a surface having an RMS of at least a hundred nanometers and a second bonding layer over the second diamond-like carbon layer.
Qian teaches an integrated-circuit system 300 having stacked first and second device wafers 304 and 306 (see Qian, Figure 3 and ¶0022). First device wafer 304 includes first semiconductor layer 310 and first metal stack 312, while second device wafer 306 includes second semiconductor layer 314 and second metal stack 316. The first and second device wafers are joined at bonding interface 308 (see Qian, Figure 3 and ¶0022-0023).
Qian therefore teaches a second semiconductor substrate positioned in a stacked relationship with a first semiconductor substrate, corresponding to second semiconductor layer 314 of second device wafer 306.
Qian further teaches a second transistor device on the second semiconductor substrate. Specifically, semiconductor layer 314 includes semiconductor regions 318 and 320. Semiconductor region 318 includes a CMOS imaging array having transistors, including transistor source and drain regions (see Qian, Figure 3 and ¶0024). Qian’s Figure 8 more specifically illustrates transfer transistor T1, reset transistor T2, source-follower transistor T3, and select transistor T4 of the CMOS imaging array.
Qian further teaches third and fourth metal layers over the second transistor device and a via extending between the metal layers. Second metal stack 316 includes multiple metal-interconnect layers M1, M2, and M3 separated by dielectric layer 328. See Qian, Figure 3 and ¶0022 and 0025). Any two successive layers of Qian’s second metal stack 316, such as layers M1 and M2, correspond to the claimed third and overlying fourth metal layers. Qian further illustrates and describes vias within the metal stacks, including vias 333B in metal stack 316 and vias 406 extending between metallizations 404 (see Qian, Figures 3 and 4 and ¶0027-0031). Accordingly, Qian teaches or at least suggests a via extending between vertically adjacent metal layers of the second metal stack.
Qian explains that stacked three-dimensional integrated circuits are used to increase circuit performance and density, improve form factor, reduce cost, and reduce the footprint of an integrated-circuit system. Qian also identifies stacking memory and processor chips on other active semiconductor chips as suitable implementations (see Qian, ¶0004).
It would have been obvious to one of ordinary skill in the art to further modify the combined semiconductor structure of Chiu and Francis by stacking a second semiconductor device structure over the first semiconductor device structure, with the second structure having a second semiconductor substrate, a second transistor device, and a second multilayer metal-interconnect structure, as taught by Qian.
A person of ordinary skill would have been motivated to make this modification to obtain the expressly identified advantages of Qian’s stacked integrated-circuit arrangement, including increased circuit performance and density, improved form factor, and reduced device footprint (see Qian ¶0004). The combination would have involved applying Qian’s known stacked-device architecture to the semiconductor device and interconnect structure of Chiu and would have produced the predictable result of a compact semiconductor structure containing first and second active device dies, each having an associated multilayer interconnect structure.
It further would have been obvious to provide the second device structure with a second diamond-like-carbon heat-spreading layer and a second bonding layer of the type taught by Francis. Both the first and second transistor-containing device structures generate heat during operation. Applying Francis’s known heat-spreading arrangement to each active device structure would predictably spread and dissipate heat generated by each respective device.
Francis itself supports this repeated-layer modification. Francis’s claim 16 expressly teaches an arrangement having a first diamond layer and first bonding layer associated with a first substrate and a second diamond layer and second bonding layer associated with a second substrate. Francis’s Figures 7(e)-7(g) and ¶0050-0052) similarly teach first and second diamond films 701 and 711, respective bonding layers 722 and 732, and stacking additional diamond and bonding layers by repeated application. Thus, providing respective heat-spreading and bonding layers for Qian’s two active device structures would have been a predictable application of Francis’s disclosed repeated diamond-layer/bonding-layer arrangement.
The second diamond-like-carbon layer would have the same disclosed roughness characteristics as the first diamond-like-carbon layer. Francis teaches diamond films having thicknesses between 1 and 1,000 micrometers and RMS surface roughness values reaching 10 percent of the film thickness (see Francis, ¶0018 and 0055). The disclosed range therefore encompasses a RMS roughness of at least hundred nanometers for both the first and second heat-spreading layers.
Providing the Francis heat-spreading and bonding arrangement for each of the two active device structures taught by Qian would also constitute duplication of a known arrangement to perform the same heat-dissipation and bonding functions for each heat-generating device structure. Such duplication would have produced the predictable result of providing heat spreading and a bonding surface for each of the stacked active devices, and no unexpected result is apparent from the claimed duplication.
Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of Chiu, Francis, and Qian to arrive at the semiconductor structure recited in claim 25.
Regarding claim 28, Chiu teaches a semiconductor structure having a semiconductor device and a multilayer metal interconnect structure. Qian teaches first and second semiconductor device wafers 304 and 306, respective semiconductor layers 310 and 314, respective metal stacks 312 and 316, and bonding interface 308 between the two device wafers. Francis teaches diamond-based thermal-dissipation layers and bonding layers formed over those diamond layers. Accordingly, the combination teaches the semiconductor structure of claim 25.
However, Chiu and Qian do not teach wherein the first bonding layer is AlN or c-BN, and the second bonding layer is AlN or c-BN.
Francis expressly identifies aluminum nitride as a suitable material for a bonding layer formed over a diamond layer. Francis further teaches an embodiment having two diamond films 701 and 711 and two respective bonding layers 722 and 732 deposited over the diamond films before the structures are bonded together. See Francis, Figures 7(e)-7(g), the corresponding description, and claim 31.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form both the first and second bonding layers of the previously modified Chiu structure from aluminum nitride, as expressly taught by Francis.
One of ordinary skill would have been motivated to select aluminum nitride for both bonding layers because Francis identifies aluminum nitride as a suitable bonding material based on its ability to adhere to diamond and an adjacent substrate and based on its bonding temperature, operating temperature, and electrical and thermal properties. Using the same known bonding material for both corresponding bonding layers would also have provided compatible interfaces and predictable bonding and thermal characteristics.
Because claim 28 recites “AlN or c-BN,” Francis’s disclosure of AlN satisfies the claimed alternative.
Regarding claim 29, Chiu teaches a semiconductor device having a multilayer interconnect structure. Qian teaches a stacked semiconductor structure having first and second semiconductor device wafers, respective semiconductor layers and metal stacks, and a bonding interface between the device wafers. Francis teaches forming diamond-based thermal-dissipation layers and bonding layers over the diamond layers. Therefore, the combination teaches the semiconductor structure of claim 25.
However, Chiu as previously modified do not teach a heat sink disposed on the second bonding layer.
Francis teaches heat-sink substrate 621 disposed directly adjacent bonding layer 611. Francis explains that bonding layer 611 is activated by heating or curing to attach diamond film 601 to heat-sink substrate 621 (see Francis, Figure 6(a), ¶0046).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispose Francis’s heat sink 621 on the second bonding layer of the previously modified Chiu semiconductor structure.
One of ordinary skill would have been motivated to make this modification because Francis teaches that the heat sink conducts heat away from the diamond thermal-dissipation layer and the associated electronic device. Positioning the heat sink on the outer second bonding layer would provide a direct thermal path from the second diamond-like carbon layer through the second bonding layer to the heat sink, thereby improving heat removal and reducing the operating temperature of the stacked semiconductor structure.
Regarding claim 30, Chiu teaches a semiconductor device having a multilayer interconnect structure. Francis teaches a diamond thermal-dissipation layer and an overlying bonding layer. Qian teaches a stacked semiconductor structure having first and second semiconductor device wafers 304 and 306 and a bonding interface 308 between the device wafers. Therefore, the combination teaches the semiconductor structure of claim 25, including a second semiconductor substrate disposed over the first bonding layer.
However, Chiu as previously modified does not teach that the second semiconductor substrate interfaces the first bonding layer.
Francis teaches placing substrate 621 directly adjacent bonding layer 611 so that substrate 621 interfaces the exposed surface of bonding layer 611. The bonding layer is subsequently activated to attach the diamond layer to substrate 621 (see Francis, Figure 6(a), ¶0046).
Qian further teaches that second device wafer 306 is joined to first device wafer 304 at bonding interface 308. Qian’s Figure 3 shows the surface of second device wafer 306 directly interfacing the bonding interface. Qian also teaches that the two device wafers may be bonded through the corresponding dielectric layers at bonding interface 308 (see Qian, Figure 3 and ¶0022-0024).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange Qian’s second semiconductor substrate so that it directly interfaces Francis’s first bonding layer in the combined stacked semiconductor structure.
One of ordinary skill would have been motivated to make this modification because Francis teaches that direct placement of the substrate against the bonding layer permits the bonding layer to secure the substrate to the underlying diamond layer, while Qian teaches directly bonding semiconductor device wafers to form a mechanically integrated stacked semiconductor structure. The proposed arrangement would predictably provide a secure bonding interface and effective thermal contact between the second semiconductor substrate and the underlying thermal-dissipation structure.
Claims 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2014/0225258 to Chiu et al. (Chiu) in view of US Pub # 2007/0269604 to Francis et al. (Francis) in view of US Pub # 2015/0349004 to Qian et al. (Qian) and further in view of US Pat# 5,559,367 to Cohen et al. (Cohen).
Regarding claim 26, Chiu teaches semiconductor devices and multilayer interconnect structures having multiple metal layers M1-Mn, metal lines 36, and vias 40 extending between adjacent metal layers. Francis teaches diamond and diamond-like carbon thermal-dissipation layers and bonding layers formed over the diamond layers. Qian teaches a stacked semiconductor structure having first and second device wafers 304 and 306, respective semiconductor layers 310 and 314, respective metal stacks 312 and 316, and bonding interface 308 between the device wafers. Therefore, Chiu in view of Francis and Qian teaches the semiconductor structure of claim 25.
However, the combination of Chiu, Francis, and Qian does not expressly teach a third via extending through both the second diamond-like carbon layer and the second bonding layer.
Cohen teaches forming openings and metal feedthroughs through diamond-like carbon material in a semiconductor interconnect structure (col. 5, lines 1-22). In Figure 1, Cohen teaches metal feedthrough 24 extending through diamond-like carbon layer 20 to electrically connect different metal levels (col. 5, lines 13-22). In Figure 3, Cohen teaches an interlevel metal-filled via 45 extending through diamond-like carbon material 46 between metal interconnect levels 42 and 43 (col. 6, lines 5-22).
Qian additionally teaches forming conductive openings through overlying layers of a stacked semiconductor structure. Specifically, Qian teaches opening 348 extending from an outer surface of second device wafer 306, through layers of the second device wafer and bonding interface 308, to expose conductor 356. The opening is subsequently lined and filled with metal to form interconnect 351 (see Qian, Figures 3 and 6D-6G and ¶0030 and 0036-0038).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the previously modified Chiu semiconductor structure by extending Qian’s conductive via through the second bonding layer and second diamond-like carbon layer according to Cohen’s known technique for forming metal-filled vias through diamond-like carbon.
One of ordinary skill would have been motivated to make this modification to provide electrical access to the underlying second metal stack while retaining the thermal-dissipation and dielectric properties of the second diamond-like carbon layer. Qian teaches using such vertical interconnects to electrically couple buried conductors in a stacked semiconductor structure, and Cohen teaches that metal-filled openings may be formed through DLC material for that purpose (col. 6, lines 34-67).
Regarding claim 27, Chiu in view of Francis, Qian, and Cohen teaches the semiconductor structure of claim 26, including a third via extending through the second diamond-like carbon layer and the second bonding layer, as set forth above.
However, the combination does not expressly teach a fourth via extending through the first diamond-like carbon layer and the first bonding layer.
Qian teaches forming multiple separate conductive openings in its stacked semiconductor structure. In particular, Qian teaches openings 334 and 348 extending through layers of the stacked structure and through bonding interface 308. Qian teaches that these openings may be formed simultaneously, lined with barrier metal 340, and filled with conductive metal to form separate conductive paths, including interconnect 351 (see Qian, Figures 3 and 6D-6G and ¶0027, 0030 and 0036-0038).
Cohen teaches forming metal-filled vias and feedthroughs through diamond-like carbon material, including metal feedthrough 24 through DLC layer 20 and interlevel via 45 through DLC material 46.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an additional fourth via through the first bonding layer and first diamond-like carbon layer of the Chiu-Francis-Qian structure according to the via teachings of Qian and Cohen.
One of ordinary skill would have been motivated to provide this additional via to establish a separate electrical connection to the first metal stack. Qian teaches using multiple conductive openings to access and electrically couple different conductors within a stacked semiconductor structure, while Cohen teaches forming such conductive feedthroughs through DLC material. Providing corresponding vias through the first and second sides would have been a predictable use of known via structures to provide electrical access to both interconnect stacks.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 9,431,368 to Enquist et al., US Pub # 2003/0147227 to Egitto et al., US Pat # 8,803,316 to Lin et al., US Pat # 8,802,504 to Hou et al. US Pat # 7,339,791 to Hoover et al.
Enquist teaches a bonding method comprising a substrate 10 has a upper surface 11 having a surface planarity on surface 11 is deposited a film 12 having a thickness greater than the surface non-planarity of surface 11, film 12 has a good thermal conductivity and a high dielectric constant, such as SiO.sub.2, diamond or diamond-like carbon (DLC), depositing film 12, polish upper surface 13, a substrate 16, film 17 formed of one or more layers with one or more polishing operations, surfaces 18 and 12 are brought into contact with each other (shown by the arrows in FIG. 3) and then a bond between surfaces 18 and 13 is formed.
Egitto discloses an electronic package 10, the electronic package 10 includes an electronic device, such as a semiconductor chip 12 having a first surface 14, the first surface including a plurality of contact members 16, the electronic package includes a multi-layered interconnect structure 18, preferably an organic chip carrier, adapted for electrically interconnecting the semiconductor chip 12 to an electronic device such as a circuitized substrate 100, the multi-layered interconnect structure 18 includes a thermally conductive layer 22 having first and second opposing surfaces 24 and 26, a first dielectric layer 28, which include sublayers 29, 39, 30, 31 and 32, is positioned on the first opposing surface 24 and a second dielectric layer 34 include sublayers 35, 41, 36, 37 and 38, is positioned on the second opposing surface 26.
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/MOHSEN AHMADI/Primary Examiner, Art Unit 2896
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