DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention II, Species I (FIG. 1F, claims 16, 17, and 19-35) in the reply filed on 6/8/26 is acknowledged.
Claim 18 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/8/26.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the solder material disposed between the metal layers of each of the plurality of bump structures and the corresponding second bonding structures (claim 16) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
In elected Species I (FIG. 1F), the applicant shows the solder material 109 between only
one metal layer 105, and the second bonding structure 205.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16, and 17 recites the limitation "the metal layers" in lines 11 and 2 respectively. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
In view of the 112 rejection above, claim(s) 16, 21 thru 23, and 25 thru 29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. US 2022/0367398 A1. Chen discloses (see, for example, FIG. 5A-5J) a method comprising a method of fabricating a vertically stacked semiconductor device, comprising: forming an intermediate redistribution layer (RDL) pad 222 over a backside surface 202a of a first semiconductor substrate 202 of a first semiconductor device structure 20; forming a plurality of bump structures 200 over the intermediate RDL pad 222, wherein each of the plurality of bump structure 200 comprises a barrier layer 244 over the intermediate RDL pad 222 and a metal layer 246 over the barrier layer 244, and the barrier layer 244 comprises a material having less solder wettability than the material of the metal layer 246; aligning the first semiconductor device structure 10 with a second semiconductor device structure 20 such that each of the plurality of bump structures 200 is aligned with a corresponding second bonding structure 146 of the second semiconductor device structure 20 and a solder material 250 is disposed between the metal layers 246/146 of each of the plurality of bump structures and the corresponding second bonding structures 146; and performing a reflow process to form a plurality of solder joints 250 extending between each of the plurality of bump structures 200 and the corresponding second bonding structures 146 of the second semiconductor device structure 10.
Regarding the limitation “the barrier layer comprises a material having less solder
wettability than the material of the metal layer;”, see, for example, paragraph [0044] wherein Chen discloses metal layer 246 including copper, etc., and in paragraph [0032], Chen discloses barrier layer 244 including nickel, etc. Nickel has less solder wettability than copper since copper bonds much better to solder because of oxidation.
Regarding claims 21, and 28, see, for example, paragraph [0044] wherein Chen discloses
metal layer 246 including copper, etc., and in paragraph [0032], Chen discloses barrier layer 244 including nickel, etc.
Regarding claims 22, and 29, see, for example, FIG. 5D wherein Chen discloses intermetallic materials 252/152.
Regarding claim 23, see, for example, FIG. 5C wherein Chen discloses the second bonding structure 146 being a single metal portion.
Regarding claim 25, see, for example, FIG. 5C wherein Chen discloses the width dimension of the barrier layer 244 being greater than a width dimension of the metal layer 246.
Regarding claim 26, see, for example, FIG. 5C wherein Chen discloses a solder material layers 148/248, and the barrier layers 144/244 constrains solder wetting along a sidewall of each of the plurality of bump structures during the reflow process.
Regarding claim 27, Chen discloses (see, for example, FIG. 5A-5J) a method of fabricating a vertically stacked semiconductor device, comprising: forming an intermediate redistribution layer (RDL) pad 222 over a backside surface 202a of a first semiconductor substrate 202; forming a bump structure 200 over the intermediate RDL pad 222, wherein the bump structure 200 comprises a barrier layer 244 over the intermediate RDL pad 222 and a metal layer 246 over the barrier layer 244, and a solder wettability of the metal layer 246 is greater than a solder wettability of the barrier layer 244; forming a solder material layer 250 over the metal layer 246 of the bump structure 200; aligning the first semiconductor substrate 202 with a second semiconductor device structure 100 such that the solder material layer 250 contacts a second bonding structure 146 of the second semiconductor device structure 100; and performing a reflow process to form a solder joint 250 extending between the bump structure 200 and the second bonding structure 146, wherein the barrier layer 244 constrains solder wetting along a sidewall of the bump structure 200 during the reflow process. Regarding the limitation “a solder wettability of the metal layer is greater than a solder wettability of the barrier layer;”, see, for example, paragraph [[0044] wherein Chen discloses metal layer 246 including copper, etc., and in paragraph [0032], Chen discloses barrier layer 244 including nickel, etc. Copper has a greater solder wettability than nickel.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17, 20, 24, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Chen et al. US 2022/0367398 A1 as applied to claims 1 above. Chen discloses (see, for example, FIG. 5D) providing a solder material 250 over each of the metal layers 246/146 of each of the plurality of bump structures 200. In paragraph [0044], Chen discloses the second bonding structure 146 includes a metal portion such as copper, etc. In FIG. 5J, Chen discloses the solder material 250 being in contact with metal portions 246/146 being in contact with one another. Chen does not clearly disclose the metal layers of each of the plurality of bump structures have a first thickness, the metal portions of the second bonding structures have a second thickness, and the solder material layers have a third thickness, and a sum of the first thickness and the second thickness is equal to or greater than one half of the third thickness. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the metal layers of each of the plurality of bump structures have a first thickness, the metal portions of the second bonding structures have a second thickness, and the solder material layers have a third thickness, and a sum of the first thickness and the second thickness is equal to or greater than one half of the third thickness to prevent the risk of the movement of the solder layer, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 20, Chen discloses (see, for example, paragraph [0032]) an electroplating process for forming the bump structures. Chen does the expressly disclose the intermediate RDL pads being formed via electroplating; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to from the RDL pads via electroplating in order to form pads with excellent uniformity and to maximize the control over the thickness of the intermediate RDL pads.
Regarding claim 24, and 30, Chen does not expressly disclose a thickness of the intermediate RDL pad is greater than a thickness of the metal layer. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a thickness of the intermediate RDL pad being greater than a thickness of the metal layer in order to minimize mechanical stress and current density.
Claim(s) 19, and 31 thru 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 2022/0367398 A1 as applied to claims 16, 21-23, and 25-29 above, and further in view of Jo et al. US 2024/0170464 A1. Chen discloses (see, for example, FIG 5J) the bump structures 200 having the same size and shape, but does not clearly disclose a plurality of intermediate RDL pads having different sizes or shapes are formed over the backside surface of the first semiconductor substrate; however, Jo discloses (see, for example, 2) a method comprising a plurality of intermediate RDL pads 150 wherein the plurality of intermediate RDL pads 150 have different sizes. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a plurality of intermediate RDL pads having different sizes or shapes are formed over the backside surface of the first semiconductor substrate in order to accommodate different sizes and shapes that fit within the limited space of a semiconductor device according the preferences of the user. Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955), and a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 31, see, the rejection for claims 16, and 19 above, and FIG. 2 wherein Jo discloses a first intermediate redistribution layer 150, and a second intermediate redistribution layer 150 having different sizes.
Regarding claim 32, see, for example, FIG. 2 wherein Jo discloses the bump structures AA having same critical dimensions.
Regarding claim 33, and 34, see, for example, FIG. 2 wherein Jo discloses a plurality of bump structures AA, which are conductive structures that are capable of transmitting signals between substrates of a semiconductor device. Chen in view of Jo does not expressly disclose power signals and data signals; however, it has been held that the recitation that an element is “capable of” performing a function (i.e. transmitting power signals and data signals) is not a positive limitation but only requires the ability of so perform. It does not constitute a limitation in any patentable sense. In re Hutchison, 69 USPQ 138.
Regarding claim 35, see, for example, FIG. 5C wherein Chen discloses the width dimension of the barrier layer 244 being greater than a width dimension of the metal layer 246.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
June 29, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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