DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 4/22/2024 and 1/16/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwak et al. US PGPub. 2019/0051831.
Regarding claim 1, Kwak teaches a test panel (10, fig. 1 and 9) [0038] comprising: a pixel (RP, GP, BP, fig. 9; collectively called P) [0053]; a first test element (TT1, fig. 9) [0054] connected to the pixel (P), the first test element (TT1; fig. 6-7A) including a gate electrode (TT_G, fig. 6-7A) [0085], a semiconductor layer (TT_ACT, fig. 6-7A) [0085], a first electrode (OL1, fig. 6-7A) [0085], and a second electrode (D1, fig. 6-7A) [0085] connected to the pixel (P); a test pad (TVP1, fig. 9) [0054] spaced apart from the first test element (TT1); a first connecting line (1CL, examiner’s fig. 1) connected to the first test element (TT1) and the test pad (TVP1); and a first resistive layer (R, fig. 9) [0054] in a same layer (TT_ACT acting as a resistance R) [0089] as the semiconductor layer (TT_ACT) and connecting the first electrode (OL1) and the first connecting line (1CL) spaced apart from each other (Kwak et al., fig. 9).
PNG
media_image1.png
856
751
media_image1.png
Greyscale
Examiner’s Fig. 1
Allowable Subject Matter
Claims 2-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a test panel comprising “a second resistive layer in the same layer as the semiconductor layer and connecting the first connecting line and the test pad spaced apart from each other” as recited in claim 2 in combination with the rest of the limitations of claim 1; and a test panel comprising “a connecting pad spaced apart from the second electrode and connected to the pixel; a second connecting line connected to the second electrode and the connecting pad; and a third resistive layer in the same layer as the semiconductor layer and connecting the second electrode and the second connecting line spaced apart from each other” as recited in claim 15 in combination with the rest of the limitations of claim 1.
Claims 3-14 and 16-20 are also objected to as allowable for further limiting and depending upon allowable claims 2 and 15.
Claims 21-22 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a test panel comprising “a first connecting line between the first test element and the test pad; a first resistive layer connecting the first electrode and the first connecting line; and a second resistive layer connecting the first connecting line and the test pad, wherein the first and second resistive layers are in a same layer as the semiconductor layer” as recited in claim 21; and a display device comprising “a pixel including a transistor and a light emitting element connected to the transistor” in combination with “a resistive layer connected to the connecting pad, wherein the resistive layer is formed of a same material as a semiconductor layer of the transistor and in a same layer as the semiconductor layer of the transistor” as recited in claim 22.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhao et al. US PGPub. 2022/0328598 (fig. 1) and Lee et al. US PGPub. 20231/0248938 (fig. 6) teaches a test/display panel comprising test elements and resistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NDUKA E OJEH/Primary Examiner, Art Unit 2892
Prosecution Insights