Prosecution Insights
Last updated: August 14, 2026
Application No. 18/641,881

HIGH-VOLTAGE METAL GATE DEVICE AND PROCESS METHOD FOR THE SAME

Non-Final OA §112
Filed
Apr 22, 2024
Priority
Jun 13, 2023 — CN 202310698772.6
Examiner
REAMES, MATTHEW L
Art Unit
Tech Center
Assignee
Shanghai Huali Microelectronics Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
848 granted / 1101 resolved
+17.0% vs TC avg
Strong +18% interview lift
Without
With
+18.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
51 currently pending
Career history
1128
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
43.2%
+3.2% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
33.3%
-6.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1101 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of the method in the reply filed on 6/5/2026 is acknowledged. Information Disclosure Statement The listing of references in the specification is not a proper information disclosure statement. 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the references have been cited by the examiner on form PTO-892, they have not been considered. Specification The disclosure is objected to because of the following informalities: The specification is inconsistent with respect to step 6. Paragraph 15 states: step 6: forming the a high-voltage area P-type source and drain in the auxiliary gate region by implanting ions on two sides of the second groove to form refractory silicide on the polysilicon layer; While paragraph 26 states: According to some embodiments, step 6 further includes: respectively doping source and drain region P-type in the first high-voltage area P-type diffusion region and the second high-voltage area P-type diffusion region; and respectively performing N-type doping in the source and drain regions in the first high-voltage area N-type diffusion region and the second high-voltage area N-type diffusion region. It appears the later is true since there is no gate disclose to bias the polysilicon between the two implanted it appears the two regions are formed during the formation of the high voltage source and drain in the N diffusion regions. Drawings The drawings are objected to under 37 CFR 1.83(a) because they fail to show The process elements occurring outside the auxiliary gate region method figures are inconsistent with the final device of figure 9 and the specification. Applicant show the entire gate oxide and high k removed outside the auxiliary gate region however these make up the gate dielectric of the metal gate thus the it should not be removed everywhere outside. Further the as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the doped regions are not depicted during the formation step specifically the n-type and the p-type regions must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Appropriate correction is required. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claims 3-4, 7 are not shown further how one forms the medium voltage device with the high voltage device is not shown, figure 9 is a single LDMOS must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 1-4, and 7-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As to claim 1, Applicant does not have support for only forming the oxide high-k and polysilicon in the auxiliary gate region. Paragraph 22 makes it clear that the polysilicon is also formed in the gate further the gate oxide and high-k are used for the metal gate dielectric and this is the point of their deposition . Thus, applicant does not have support for only the steps cited in only the auxiliary gate region. Claim 5 fixes this deficiency. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. a. Claim 1 recites etching back the first STI region to form a first groove in the first STI region, forming an auxiliary gate region in the first groove, and forming a metal gate region between the first high-voltage area N-type diffusion region and the second high-voltage area N-type diffusion region; recitation forming an auxiliary gate region in the first groove and forming a metal gate region between the first high-voltage area N-type diffusion region should be recites is thereby forming and thereby forming. Applicant does any additional steps to form the region and step 3 requires the deposition of the material that go into forming the metal gate and auxiliary gate. Thus, it is unclear what additional steps are needed to encompass forming an auxiliary gate region in the first groove and forming a metal gate region between the first high-voltage area N-type diffusion region and the second high-voltage area N-type diffusion region. b. Further claim 1, is unclear since step 6 recites step 6: forming, by ion implantation, a high-voltage area P-type source and a high-voltage area P-type drain in the auxiliary gate region at two sides of the second groove respectively, and forming a refractory silicide layer on the reserved polysilicon layer in the first groove. However ,there appears there is no source drain formed in the polysilicon instead the high voltage source drain are formed in the substrate in the n regions HVPDF. Specifically there is no gate biasing region 5 to form a transistor to have a source drain. It appears applicant means to recite implanting p source drains in the substrate in the n-region and simultaneously implanting the polysilicon region. c. Claims 1-10 are unclear, despite reciting A process method for a high-voltage metal gate device there is no metal gate ever formed. d. As to claim 3 and 4, it is unclear when the medium voltage device comprises the oxide it appears applicant means wherein step 1 further comprises forming a medium-voltage device region in the substrate, wherein forming the medium-voltage device region comprises forming an oxide layer. e. As to claim 5 it is unclear gate oxide and the high-k and polysilicon are the same or different from claim 1, it appears that they should be the same elements. If they are different this could be invoke written description. Allowable Subject Matter Claims 1-10 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action. Relevant prior art Chuang 20160141298 recesses the STI to form a memory. Koshimizu 20220393027 forms a diode as an auxiliary gate/field plate (items 17 18 and 19). Ma 20160005858 in a similar manner forms a diode 118 acting as a field plate/ auxiliary gate. Yu 8729631 teaches recessing the STI to form field plates. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW L. REAMES/ Primary Examiner Art Unit 2896 /MATTHEW L REAMES/ Primary Examiner, Art Unit 2896
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Prosecution Timeline

Apr 22, 2024
Application Filed
Jul 20, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
95%
With Interview (+18.0%)
2y 8m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1101 resolved cases by this examiner. Grant probability derived from career allowance rate.

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