DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/22/2024, 9/16/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 8-10, 12, 14-15, 17-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (US 2020/0098764).
Regarding claim 1, Wang discloses, in at least figures 1-5 and related text, a device layout, comprising:
a memory cell (101a, [14], [15]) including:
a first active semiconductor region (112, [19]) for first type transistors ([19]), wherein the first active semiconductor region (112, [19]) is disposed lengthwise along a first direction (y direction, figures);
a second active semiconductor region (110, [19]) for second type transistors ([19]), wherein the second type transistors ([19]) are different than the first type transistors ([19]) and the second active semiconductor region (110, [19]) is disposed lengthwise along the first direction (y direction, figures);
a dielectric line (114, [19]) disposed between the first active semiconductor region (112, [19]) and the second active semiconductor region (110, [19]), wherein the dielectric line (114, [19]) is disposed lengthwise along the first direction (y direction, figures), a first spacing is between the dielectric line (114, [19]) and the first active semiconductor region (112, [19]) along a second direction (x direction, figures) that is different than the first direction (y direction, figures), and a second spacing is between the dielectric line (114, [19]) and the second active semiconductor region (110, [19]) along the second direction (x direction, figures); and
wherein the first active semiconductor region (112, [19]), the second active semiconductor region (110, [19]), and the dielectric line (114, [19]) each extend along the first direction (y direction, figures) across a boundary of the memory cell (figures).
Regarding claim 2, Wang discloses the device layout of claim 1 as described above.
Wang further discloses, in at least figures 1-5 and related text, the first type transistors ([19]) are p-type transistors, and the second type transistors ([19]) are n-type transistors.
Regarding claim 6, Wang discloses the device layout of claim 1 as described above.
Wang further discloses, in at least figures 1-5 and related text, the first spacing equals the second spacing (figures).
Regarding claim 8, Wang discloses the device layout of claim 1 as described above.
Wang further discloses, in at least figures 1-5 and related text, the memory cell further includes a substrate isolation structure (106, [23]) extending from the first active semiconductor region (112, [19]) to the second active semiconductor region (110, [19]); and
wherein the dielectric line (114, [19]) is disposed in the substrate isolation structure (106, [23]).
Regarding claim 9, Wang discloses the device layout of claim 1 as described above.
Wang further discloses, in at least figures 1-5 and related text, the first active semiconductor region (112, [19]) includes a first semiconductor channel region (112 under 118, figures) disposed between first semiconductor source/drain regions (124, [24]);
the second active semiconductor region (110, [19]) includes a second semiconductor channel region (110 under 118, figures) disposed between second semiconductor source/drain regions (122, [24]);
the dielectric line (114, [19]) is disposed between the first semiconductor channel region (112 under 118, figures) and the second semiconductor channel region (110 under 118, figures); and
the dielectric line (114, [19]) is disposed between the first semiconductor source/drain regions (124, [24]) and the second semiconductor source/drain regions (122, [24]).
Regarding claim 10, Wang discloses the device layout of claim 1 as described above.
Wang further discloses, in at least figures 1-5 and related text, a gate line (118, [24]) disposed on the first active semiconductor region (112, [19]), the second active semiconductor region (110, [19]), and the dielectric line (114, [19]), wherein the gate line (118, [24]) is disposed lengthwise along the second direction (x direction, figures).
Regarding claim 12, Wang discloses, in at least figures 1-5 and related text, a device layout, comprising:
a logic standard cell (101d, [14], [15]) including first active semiconductor regions (110/112, [19]) oriented lengthwise along a first direction (y direction, figures) and first dielectric lines (116, [17]) oriented along the first direction (y direction, figures), wherein each of the first active semiconductor regions (110/112, [19]) is disposed between and spaced from a respective pair of first dielectric lines (y direction, figures) along a second direction (x direction, figures) different than the first direction (y direction, figures);
a memory cell (101a, [14], [15]) including second active semiconductor regions (110/112, [19]) oriented lengthwise along the first direction (y direction, figures) and second dielectric lines (116, [17]) oriented along the first direction (y direction, figures), wherein each of the second active semiconductor regions (110/112, [19]) is disposed between and spaced from a respective pair of second dielectric lines (116, [17]) along the second direction (x direction, figures); and
wherein each of the first dielectric lines (116, [17]) extends along the first direction (y direction, figures) across a boundary of the logic standard cell (101d, [14], [15]) and each of the second dielectric lines (116, [17]) extends along the first direction (y direction, figures) across a boundary of the memory cell (101a, [14], [15]).
Regarding claim 14, Wang discloses the device layout of claim 12 as described above.
Wang further discloses, in at least figures 1-5 and related text, each of the second active semiconductor regions (110/112, [19]) extends along the first direction (y direction, figures) across the boundary of the memory cell (101a, [14], [15]).
Regarding claim 15, Wang discloses the device layout of claim 12 as described above.
Wang further discloses, in at least figures 1-5 and related text, each of the first active semiconductor regions (110/112, [19]) extends along the first direction (y direction, figures) across the boundary of the logic standard cell (101d, [14], [15]).
Regarding claim 17, Wang discloses the device layout of claim 12 as described above.
Wang further discloses, in at least figures 1-5 and related text, the boundary of the logic standard cell (101d, [14], [15]) is a first boundary of the logic standard cell (101d, [14], [15]) that extends lengthwise along the second direction (x direction, figures) and the boundary of the memory cell (101a, [14], [15]) is a first boundary of the memory cell (101a, [14], [15]) that extends lengthwise along the second direction (x direction, figures);
at least one of the first dielectric lines (116, [17]) is disposed in the logic standard cell (101d, [14], [15]) and at least two of the first dielectric lines (116, [17]) are disposed on a respective second boundary of the logic standard cell (101d, [14], [15]) that extends lengthwise along the first direction (y direction, figures); and
at least one of the second dielectric lines (116, [17]) is disposed in the memory cell (101a, [14], [15]) and at least two of the second dielectric lines (116, [17]) are disposed on a respective second boundary of the memory cell (101a, [14], [15]) that extends lengthwise along the first direction (y direction, figures).
Regarding claim 18, Wang discloses, in at least figures 1-5 and related text, a device layout, comprising:
a memory cell (101a, [14], [15]) having a first memory cell boundary (left boundary of 101a, figures), a second memory cell boundary (right boundary of 101a, figures), a third memory cell boundary (bottom boundary of 101a, figures), and a fourth memory cell boundary (top boundary of 101a, figures), wherein the first memory cell boundary (left boundary of 101a, figures) and the second memory cell boundary (right boundary of 101a, figures) extend lengthwise along a first direction (y direction, figures), the third memory cell boundary (bottom boundary of 101a, figures) and the fourth memory cell boundary (top boundary of 101a, figures) extend lengthwise along a second direction (x direction, figures) that is different than the first direction (y direction, figures), and the third memory cell boundary (bottom boundary of 101a, figures) and the fourth memory cell boundary (top boundary of 101a, figures) extend from the first memory cell boundary (left boundary of 101a, figures) to the second memory cell boundary (right boundary of 101a, figures), wherein the memory cell further includes:
dielectric lines (114/116, [17], [19]) that extend lengthwise along the first direction (y direction, figures), wherein the dielectric lines (114/116, [17], [19]) include a first memory cell boundary dielectric line (left 116, [17], figures) disposed on the first memory cell boundary (left boundary of 101a, figures), a second memory cell boundary dielectric line (right 116, [17], figures) disposed on the second memory cell boundary (right boundary of 101a, figures), and inner memory cell dielectric lines (114, [19]) disposed in the memory cell (101a, [14], [15]) and between the first memory cell boundary dielectric line (left 116, [17], figures) and the second memory cell boundary dielectric line (right 116, [17], figures), and
active region lines (110, [19]) that extend lengthwise along the first direction (y direction, figures), wherein each active region line (110, [19]) is disposed between a respective pair of the dielectric lines (114/116, [17], [19]) along the second direction (x direction, figures).
Regarding claim 20, Wang discloses the device layout of claim 18 as described above.
Wang further discloses, in at least figures 1-5 and related text, the memory cell is a first memory cell (101a, [14], [15]), the device layout further comprising:
a second memory cell (101b, [14], [15]) having the fourth memory cell boundary (bottom boundary of 101b, figures), a fifth memory cell boundary (top boundary of 101b, figures), a sixth memory cell boundary (left boundary of 101b, figures), and a seventh memory cell boundary (right boundary of 101b, figures);
wherein the fifth memory cell boundary (top boundary of 101b, figures) extends lengthwise along the second direction (x direction, figures), the sixth memory cell boundary (left boundary of 101b, figures) and the seventh memory cell boundary (right boundary of 101b, figures) extend lengthwise along the first direction (y direction, figures), and the fourth memory cell boundary (bottom boundary of 101b, figures) and the fifth memory cell boundary (top boundary of 101b, figures) extend from the sixth memory cell boundary (left boundary of 101b, figures) to the seventh memory cell boundary (right boundary of 101b, figures);
wherein the second memory cell (101b, [14], [15]) further includes the dielectric lines (114/116, [17], [19]), wherein the first memory cell boundary dielectric line (left 116, [17], figures) is disposed on the sixth memory cell boundary (left boundary of 101b, figures), the second memory cell boundary dielectric line (right 116, [17], figures) is disposed on the seventh memory cell boundary (right boundary of 101b, figures), and the inner memory cell dielectric lines (114, [19]) are disposed in the second memory cell (101b, [14], [15]); and
wherein the second memory cell (101b, [14], [15]) further includes the active region lines (110, [19]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2020/0098764) in view of Liaw (US 2021/0057023).
Regarding claim 11, Wang discloses the device layout of claim 10 as described above.
Wang does not explicitly disclose in a cross-sectional view along the second direction, the gate line wraps the dielectric line.
Liaw teaches, in at least figures 2-4 and related text, the device comprising in a cross-sectional view along the second direction (x direction, figures), the gate line (262/264, [36]) wraps the dielectric line (232, [30]), for the purpose of providing SRAM cell including a first plurality of gate-all-around (GAA) transistors, a second SRAM cell including a second plurality of GAA transistors, and a dielectric fin between the first SRAM cell and the second SRAM cell ([49]) thereby improving density of integration.
Wang and Liaw are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Wang to have in a cross-sectional view along the second direction, the gate line wrapping the dielectric line, as taught by Liaw, for the purpose of providing SRAM cell including a first plurality of gate-all-around (GAA) transistors, a second SRAM cell including a second plurality of GAA transistors, and a dielectric fin between the first SRAM cell and the second SRAM cell ([49], Liaw) thereby improving density of integration.
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 3 that recite "the width W3 is different than the width W2 and the width W2 is different than the width W1" in combination with other elements of the base claims 1 and 3.
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 6 that recite "a second dielectric line disposed between the second active semiconductor region and the third active semiconductor region, wherein the second dielectric line is disposed lengthwise along the first direction, a third spacing is between the second dielectric line and the second active semiconductor region along the second direction, and a fourth spacing is between the second dielectric line and the third active semiconductor region along the second direction" in combination with other elements of the base claims 1 and 6.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 12 and 13 that recite "the first width is greater than the second width" in combination with other elements of the base claims 12 and 13.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 12 and 16 that recite "some of the first active semiconductor regions extend along the first direction and do not cross the boundary of the logic standard cell" in combination with other elements of the base claims 12 and 16.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 18 and 19 that recite "the first dielectric lines have a first width along the second direction, the second dielectric lines have a second width along the second direction, and the second width is greater than the first width" in combination with other elements of the base claims 18 and 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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