DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-10, in the reply filed on 07/22/2026 is acknowledged.
Status of the Application
Claims 1-10 remain pending in this application. Acknowledgement is made of the amendment received 07/22/2026. Claims 11-20 are canceled.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “interface” in the limitation “the second metal line is integrally formed so as to have no interface therein” of claim 3 appears to be used to mean “void” or “seam” while an accepted meaning of “interface” is “a surface forming a common boundary between two portions of matter or space.” The term is indefinite because the specification does not clearly redefine the term.
Further, the limitation “the second metal line is integrally formed so as to have no interface therein” does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. For example, it is unclear if the claim is intended to limit the second metal line to a body having no seams or voids between different materials, a body having no seams or voids between separately formed portions of a same material, or some other meaning.
For the purposes of compact prosecution, the examiner is interpreting the limitation to have intended to state “wherein the second metal line includes a first portion above the second dielectric layer and a second portion extending into the through hole, wherein the first and second portions are a continuous body of a same material”. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required.
Regarding claim 10, it recites the limitation “a through hole” in line 3. Claim 1, from which claim 10 depends, previously recites “a through hole”, and it is unclear whether “a through hole” recited in claim 10 refers to the through hole of claim 1 or to a different through hole, therefore, there is insufficient antecedent basis for this limitation in the claim.
Additionally, claim 10 recites the limitation "the third dielectric layer, the second buffer layer, the second metal line, the first buffer layer, and a top portion of the second dielectric layer have a through hole" in lines 1 to 3, which does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. For example, it is unclear if the claim requires a single through hole that is common to each of the listed layers, or if each of the listed layers is required to have a through hole, or some other meaning.
Further, it is unclear if a through hole in “a top portion of the second dielectric layer” must pass through the entire thickness of the second dielectric layer, which the term “through hole” appears to require, or only into a top portion of the second dielectric layer, which is further is unclear as to what constitutes “a top portion”; for example it is unclear if the claim is intended to limit a through hole only partially penetrating the second dielectric layer, or if a through hole must at least penetrate into the second dielectric layer, or some other meaning.
For the purposes of compact prosecution, the examiner is interpreting the limitation to have intended to state “at least one of the third dielectric layer, the second buffer layer, the second metal line, the first buffer layer, and the top surface of the second dielectric layer have another through hole”. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito et al (US 20010045651 A1, hereafter Saito).
Regarding claim 1, Saito discloses: A semiconductor structure (Saito fig 13a-20, ¶0121), comprising:
a first dielectric layer (Saito 23, ¶0123, 0144) having a first metal line (Saito 26, ¶0128, 0140, under a broadest reasonable interpretation (BRI) of “metal line”, wiring 26 is at least a line of metal extending along 25) in a top surface of the first dielectric layer (Saito fig 14b, 20, ¶0124);
a protection layer (Saito 28, ¶0137, under a BRI of “protection layer”, 28 is an etch stop, therefore at least protecting 23 and 26 from etching) located on the first dielectric layer (Saito fig 15b, 20, ¶0137);
a second dielectric layer (Saito 29, ¶0137, 0144) located on the protection layer (Saito fig 15b, 20, ¶0137), wherein the second dielectric layer and the protection layer have a through hole (Saito 30, 34, ¶0138, 0140)(Saito fig 17b, ¶0138, 0140), and the first metal line is below the through hole (Saito fig 17b, 20);
a first buffer layer (Saito 35a, ¶0146, “titanium nitride”, applicant discloses that suitable materials for a buffer layer include “titanium nitride (TiN)”, spec ¶0034) located on a top surface of the second dielectric layer, a sidewall of the through hole, and a top surface of the first metal line (Saito fig 18b, 20, ¶0145-0147); and
a second metal line (Saito 35, 35b, 35c, ¶0147) located on the first buffer layer and extending into the through hole (Saito fig 18b, 20, ¶0147).
Regarding claim 2, Saito discloses: The semiconductor structure of claim 1, wherein the second metal line (Saito 35, 35b) has a bottom portion (Saito fig 18b, 20, portion of 35b within 30) surrounded by the second dielectric layer (Saito 29) and the protection layer (Saito 28)(Saito fig 18b, 20, ¶0146).
Regarding claim 3, Saito discloses: The semiconductor structure of claim 1, wherein the second metal line is integrally formed so as to have no interface therein (as best understood to mean “wherein the second metal line includes a first portion above the second dielectric layer and a second portion extending into the through hole, wherein the first and second portions are a continuous body of a same material”)(wherein the second metal line (Saito 35, 35b) includes a first portion above the second dielectric layer (Saito 29)(Saito fig 17b, 18b, 20, portion of 35b within 34) and a second portion extending into the through hole (Saito 30)(Saito fig 18b, 20, portion of 35b within 30), wherein the first and second portions are a continuous body of a same material (Saito ¶0146-0148, fig 18b, 20)).
Regarding claim 6, Saito discloses: The semiconductor structure of claim 1, wherein a material of the first buffer layer (Saito 35a) comprises titanium nitride (Saito ¶0146, “titanium nitride”).
Regarding claim 7, Saito discloses: The semiconductor structure of claim 1, further comprising: a second buffer layer (Saito 39a, ¶0103, 0155, “titanium nitride”, applicant discloses that suitable materials for a buffer layer include “titanium nitride (TiN)”, spec ¶0034, 39a being similar to 31a) located on a top surface of the second metal line (Saito 35, 35b, 35c)(Saito fig 19, 20).
Regarding claim 8, Saito discloses: The semiconductor structure of claim 7, wherein a material of the second buffer layer (Saito 39a, ¶0103, 0155, “titanium nitride”) is the same as a material of the first buffer layer (Saito 35a, ¶0146, “titanium nitride”).
Regarding claim 9, Saito discloses: The semiconductor structure of claim 7, further comprising: a third dielectric layer (Saito 41, ¶0113) located on the second buffer layer (Saito 39a)(Saito fig 20, similar to fig 11).
Regarding claim 10, Saito discloses: The semiconductor structure of claim 9, wherein (as best understood to mean “at least one of”) the third dielectric layer (Saito 41), the second buffer layer (Saito 39a), the second metal line (Saito 35, 35b, 35c), the first buffer layer (Saito 35a), and a top portion of the second dielectric layer (as best understood to mean “the top surface of the second dielectric layer”)( Saito 29, fig 18b, 20, top surface of 29) have a through hole (as best understood to mean “another through hole”)(Saito fig 11, 20, ¶0113, 0155, hole in 41 forming contact area of 40 for 43).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al (US 20010045651 A1, hereafter Saito), as applied to claim 1 above, and further in view of Yamamoto (US 20020158339 A1, hereafter Yamamoto).
Regarding claim 4, Saito teaches: The semiconductor structure of claim 1.
Saito does not teach: wherein a material of the second metal line is different from a material of the first metal line.
Saito further teaches: different materials of a wiring (Saito, ¶0022, 0194, claim 7, “copper (Cu), silver (Ag), aluminum (Al) or an alloy”).
Saito, in at least one embodiment, further teaches: a material of a first wiring (Saito 35, 35b, ¶0146, “copper”) and a material of a second wiring (Saito 40b, ¶0112, “aluminum”) are different (Saito ¶0112, 0146).
Yamamoto, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a material of a second wiring (Yamamoto 22, ¶0134, 0142, “copper-based wiring”) is different from a material of a first wiring (Yamamoto 18, ¶0142, “aluminum-based wiring”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the second metal line of Saito to comprise aluminum, and such that “a material of the second metal line is different from a material of the first metal line”, as taught by Yamamoto, in order to reduce manufacturing costs of a wiring layer while maintaining lower resistance materials where needed (Yamamoto ¶0009, 0072, 0262-0264).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to choose any number of suitable materials for the second metal line, including aluminum, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (MPEP 2144.07).
Regarding claim 5, Saito teaches: The semiconductor structure of claim 1.
Saito does not teach: wherein a material of the second metal line comprises aluminum, and a thickness of the second metal line above the first buffer layer is in a range from 700 nm to 800 nm.
Saito, in at least one embodiment, further teaches: a material of a second wiring comprises aluminum (Saito 40b, ¶0112, “aluminum”).
Yamamoto, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a material of a second wiring comprises aluminum (Yamamoto 22, ¶0134, 0142, “aluminum-based wiring”), and
a thickness of the second wiring above titanium nitride layer (Yamamoto ¶0118, 0133, “titanium nitride”) is in a range from 700 nm to 800 nm (Yamamoto ¶0118, “300-1000 nm”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the second metal line of Saito to comprise aluminum, and further to adjust a thickness of the second metal line, such that “wherein a material of the second metal line comprises aluminum, and a thickness of the second metal line above the first buffer layer is in a range from 700 nm to 800 nm”, as taught by Yamamoto, in order to reduce manufacturing costs of a wiring layer while maintaining lower resistance materials where needed (Yamamoto ¶0009, 0072, 0262-0264).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to choose any number of suitable materials for the second metal line, including aluminum, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (MPEP 2144.07). Additionally, the adjustment of thickness of a spacer is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a thickness is disclosed by Yamamoto, and therefore discovering the optimum or working range of “a thickness of the second metal line above the first buffer layer is in a range from 700 nm to 800 nm” involves only routine skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Amanapu et al (US 20200111736 A1) is cited as an example of an analogous device further having a third dielectric layer on a second buffer layer on a top surface of a second metal line.
Edelstein et al (US 6133136 A) is cited as an example of an analogous device further having a first metal line comprising Cu and a second metal line comprising Al on a TiN buffer layer.
Fujiwara et al (JP 2004031866 A) is cited as an example of an analogous device further having a second metal line formed on a TiN buffer layer and extending into a through hole.
Clampitt (US 6081033 A) is cited as an example of an analogous device further having a through hole extending through a metal line, a buffer layer, and into a dielectric layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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