DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant amended claim 16; and added claims 21-35 on 4/22/2024.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-23 and 29-35 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2015/0221654) (hereafter Kim), in view of Lee et al. (US 2016/0190017) (hereafter Lee).
Regarding claim 16, Kim discloses a semiconductor structure, comprising:
first fins (306 and 308 in Fig. 73, paragraph 0046) and second fins 302 (Fig. 73, paragraph 0136) extending from a semiconductor substrate 300 (Fig. 73, paragraph 0129);
isolation features 320 (Fig. 73, paragraph 0129) disposed over the semiconductor substrate 300 (Fig. 73) to separate the first fins (306 and 308 in Fig. 73) and the second fins 302 (Fig. 73), wherein the first fins (306 and 308 in Fig. 73) and the second fins 302 (Fig. 73) have a fin height measured from a top surface of the isolation features 320 (Fig. 73);
a first device (see “PMOS” of II in Fig. 73) over the first fins (306 and 308 in Fig. 73), the first device (see “PMOS” of II in Fig. 76) including:
a first gate stack 484 (Fig. 76, paragraph 0147) engaged with first channel regions 302 (Fig. 76) of the first fins, a first epitaxial source/drain (S/D) feature 425 (Fig. 76, paragraph 0148) disposed on opposite sides of the first channel regions 302 (Fig. 76), and first fin spacers 369 (Fig. 74, paragraph 0136) disposed on sidewalls of the first epitaxial S/D feature 425 (Fig. 74), wherein the first fin spacers 369 (Fig. 74) have a first height H4 (Fig. 74, paragraph 0136) measured from the top surface of the isolation features 320 (Fig. 73);
a second device (see “PMOS” of I in Fig. 73) over the second fins 302 (Fig. 73), the second device (see “PMOS” of I in Fig. 75) including:
a second gate stack 482 (Fig. 76, paragraph 0147) engaged with second channel regions 302 (Fig. 75) of the second fins, second epitaxial S/D features (390, 400, and 510 in Fig. 75) disposed on opposite sides of the second channel regions 302 (Fig. 75), and
second fin spacers 367 (Fig. 74, paragraph 0145) disposed on sidewalls of the second epitaxial S/D features 420 (Fig. 74), wherein the second fin spacers 367 (Fig. 74) have a second height H3 (Fig. 74, paragraph 0136) measured from the top surface of the isolation features 320 (Fig. 73) that is greater (see Fig. 74 and paragraph 0136) than the first height H4 (Fig. 74); and
an inter-layer dielectric (ILD) layer 440 (Fig. 74, paragraph 0150) over the first device (see “PMOS” of “II” region in Fig. 74) and the second device (see “PMOS” of “I” region in Fig. 74), wherein the ILD layer 440 (Fig. 74) separates the second epitaxial S/D features 420 (Fig. 74).
Kim does not disclose the first epitaxial S/D feature merges together the first fins.
Lee discloses the first epitaxial S/D feature 110 (Fig. 1B, paragraph 0017) merges together the first fins.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form the first epitaxial S/D feature merges together the first fins, as taught by Lee, since the epitaxial feature 110 (Lee, Fig. 1B, paragraph 0017) is tuned to improve device performance for a logic device.
Regarding claim 17, Kim further discloses the semiconductor structure of claim 16, wherein the first device (see paragraph 0130, wherein “the second region II of the substrate 300 may be a logic region“) is a logic device and the second device (see paragraph 0130, wherein “The first region I of the substrate 300 may be an SRAM region”) is a memory device.
Regarding claim 18, Kim further discloses the semiconductor structure of claim 16, wherein a top surface of the first epitaxial S/D feature 425 (Fig. 74) is above top surfaces of the first fins (region between second 320 and third 320 from the right corner of Fig. 74).
Regarding claim 19, Kim further discloses the semiconductor structure of claim 16, wherein a bottom surface (bottom surface of 425 contacting 395 in Fig. 74) of the first epitaxial S/D feature 425 (Fig. 74) is below a bottom surface (bottom surface of 420 contacting 410 in Fig. 74) of the second epitaxial S/D features 420 (Fig. 74).
Regarding claim 20, Kim further discloses the semiconductor structure of claim 16, wherein a width (longest horizontal length of 425 in Fig. 74) of the first epitaxial S/D feature 425 (Fig. 74) is greater than the fin height (horizontal length of region between second 320 and third 320 from the right corner of Fig. 74).
Regarding claim 21, Kim discloses a semiconductor structure comprising:
a first source/drain region (“II” region in Fig. 74) that includes:
a first semiconductor fin (region between second 320 and third 320 from the right corner of Fig. 74),
a second semiconductor fin (region between first 320 and second 320 from the right corner of Fig. 74),
a first epitaxial structure 425 (Fig. 74, paragraph 0140) disposed on the first semiconductor fin (region between second 320 and third 320 from the right corner of Fig. 74), and
a second epitaxial structure 435 (Fig. 74, paragraph 0142) disposed on the second semiconductor fin (region between first 320 and second 320 from the right corner of Fig. 74);
a second source/drain region (“I” region in Fig. 74) that includes:
a third semiconductor fin (region between second 320 and third 320 from the left corner of Fig. 74),
a fourth semiconductor fin (region between third 320 and fourth 320 from the left corner of Fig. 74),
a third epitaxial structure (left 420 in Fig. 74, paragraph 0139) disposed on the third semiconductor fin (region between second 320 and third 320 from the left corner of Fig. 74), and
a fourth epitaxial structure (right 420 in Fig. 74, paragraph 0139) disposed on the fourth semiconductor fin (region between third 320 and fourth 320 from the left corner of Fig. 74), wherein the fourth epitaxial structure (right 420 in Fig. 74) is not merged with the third epitaxial structure (left 420 in Fig. 74);
first dielectric spacers (third 369 and fourth 369 from the right corner of Fig. 74) disposed along first sidewalls of the first epitaxial structure 425 (Fig. 74), second dielectric spacers (first 369 and second 369 from the right corner of Fig. 74) disposed along second sidewalls of the second epitaxial structure 435 (Fig. 74), third dielectric spacers (third 367 and fourth 367 from the left corner of Fig. 74) disposed along third sidewalls of the third epitaxial structure (left 420 in Fig. 74), and fourth dielectric spacers (fifth 367 and sixth 367 from the left corner of Fig. 74) disposed along fourth sidewalls of the fourth epitaxial structure (right 420 in Fig. 74);
wherein the first dielectric spacers (third 369 and fourth 369 from the right corner of Fig. 74) and the second dielectric spacers (first 369 and second 369 from the right corner of Fig. 74) have a first spacer height H4 (Fig. 74, paragraph 0136), the third dielectric spacers (third 367 and fourth 367 from the left corner of Fig. 74) and the fourth dielectric spacers (fifth 367 and sixth 367 from the left corner of Fig. 74) have a second spacer height H3 (Fig. 74, paragraph 0136), and the second spacer height H3 (Fig. 74) is greater (see Fig. 74 and paragraph 0136) than the first spacer height H4 (Fig. 74); and
wherein the first source/drain region (“II” region in Fig. 74) forms a portion of a first device (“PMOS” of “II” region in Fig. 74) and the second source/drain region (“I” region in Fig. 74) forms a portion of a second device (“PMOS” of “I” region in Fig. 74).
Kim does not disclose the second epitaxial structure is merged with the first epitaxial structure
Lee discloses the second epitaxial structure (right portion of 110 in Fig. 1B, paragraph 0017) is merged with the first epitaxial structure (left portion of 110 in Fig. 1B, paragraph 0017).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form the second epitaxial structure is merged with the first epitaxial structure, as taught by Lee, since the epitaxial feature 110 (Lee, Fig. 1B, paragraph 0017) is tuned to improve device performance for a logic device.
Regarding claim 22, Kim further discloses the semiconductor structure of claim 21, wherein: the first device (see paragraph 0130, wherein “the second region II of the substrate 300 may be a logic region“) is configured to perform a logic function; and the second device (see paragraph 0130, wherein “The first region I of the substrate 300 may be an SRAM region”) is configured to perform a memory function.
Regarding claim 23, Kim further discloses the semiconductor structure of claim 21, wherein each of the first semiconductor fin 306 (Fig. 73), the second semiconductor fin 308 (Fig. 73), the third semiconductor fin (left 302 in Fig. 73), and the fourth semiconductor fin (right 302 in Fig. 73) includes silicon and germanium (see “silicon-germanium” in paragraph 0042).
Regarding claim 29, Kim in view of Lee discloses the semiconductor structure of claim 21, Kim does not disclose the first epitaxial structure and the second epitaxial structure have a first volume; the third epitaxial structure and the fourth epitaxial structure have a second volume; and the second volume is less than the first volume.
Lee discloses the first epitaxial structure (left portion of 110 in Fig. 1B) and the second epitaxial structure (right portion of 110 in Fig. 1B) have a first volume; the third epitaxial structure (left portion of 150 in Fig. 1B) and the fourth epitaxial structure (right portion of 150 in Fig. 1B) have a second volume; and the second volume (see Fig. 1B) is less than the first volume.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form the first epitaxial structure and the second epitaxial structure have a first volume; the third epitaxial structure and the fourth epitaxial structure have a second volume; and the second volume is less than the first volume, as taught by Lee, since the epitaxial feature 110 (Lee, Fig. 1B, paragraph 0017) is tuned to improve device performance for a logic device, and the epitaxial feature 150 (Lee, Fig. 1B, paragraph 0017) is tuned to improve device performance for a memory device.
Regarding claim 30, Kim discloses a device comprising:
a first transistor (see “PMOS” of II in Fig. 73) that includes first semiconductor fins 306 (Fig. 73, paragraph 0046), a first gate 474 (Fig. 73, paragraph 0146) that wraps first channel regions 306 (Fig. 73) of the first semiconductor fins, first epitaxial source/drains 405 (Fig. 74, paragraph 0140) disposed over first source/drain regions (region between second 320 and third 320 from the right corner of Fig. 74) of the first semiconductor fins, and first fin spacers 369 (Fig. 74, paragraph 0145) disposed along first sidewalls of the first epitaxial source/drains, wherein the first fin spacers 369 (Fig. 74) have a first fin spacer height H4 (Fig. 74, paragraph 0136) and the first epitaxial source/drains 405 (Fig. 74) have a first volume (volume of 405 in Fig. 74);
a second transistor (see “PMOS” of I in Fig. 73) that includes second semiconductor fins 302 (Fig. 73, paragraph 0136), a second gate 472 (Fig. 73, paragraph 0146) that wraps second channel regions 302 (Fig. 73) of the second semiconductor fins, second epitaxial source/drains 400 (Fig. 74, paragraph 0140) disposed over second source/drain regions (region between second 320 and third 320 from the left corner of Fig. 74) of the second semiconductor fins, and second fin spacers 367 (Fig. 74, paragraph 0145) disposed along second sidewalls of the second epitaxial source/drains 400 (Fig. 74), wherein the second fin spacers 367 (Fig. 74) have a second fin spacer height H3 (Fig. 74, paragraph 0136) and the second epitaxial source/drains 400 (Fig. 74) have a second volume (volume of 400 in Fig. 74); and
wherein the first fin spacer height H4 (Fig. 74) is less than (see Fig. 74 and paragraph 0136) the second fin spacer height H3 (Fig. 74).
Kim does not disclose the first volume is greater than the second volume.
Lee discloses the first volume (volume of 110 in Fig. 1B, paragraph 0017) is greater than the second volume (volume of 150 in Fig. 1B, paragraph 0017).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form the first volume being greater than the second volume, as taught by Lee, since the epitaxial feature 110 (Lee, Fig. 1B, paragraph 0017) is tuned to improve device performance for a logic device, and the epitaxial feature 150 (Lee, Fig. 1B, paragraph 0017) is tuned to improve device performance for a memory device.
Regarding claim 31, Kim further discloses the device of claim 30, wherein the first transistor (see “PMOS” of II in Fig. 73) is a first p-type transistor, and the second transistor (see “PMOS” of I in Fig. 73) is a second p-type transistor.
Regarding claim 32, Kim further discloses the device of claim 30, wherein the first source/drain regions (region between second 320 and third 320 from the right corner of Fig. 74) of the first semiconductor fins have a first sidewall height (vertical length of 405 between upper portion of 415 and lower portion of 415 in Fig. 74), the second source/drain regions (region between second 320 and third 320 from the left corner of Fig. 74) of the second semiconductor fins have a second sidewall height (vertical length of 400 between 510 and 390 in Fig. 74), and the second sidewall height (vertical length of 400 between 510 and 390 in Fig. 74) is greater than the first sidewall height (vertical length of 405 between upper portion of 415 and lower portion of 415 in Fig. 74).
Regarding claim 33, Kim further discloses the device of claim 32, further comprising a shallow trench isolation structure (320 and 440 in Figs. 74, paragraph 0145), wherein the first sidewall height (vertical length of 405 between upper portion of 415 and lower portion of 415 in Fig. 74) is less than a height (vertical length of 320 and 440 in Fig. 74) of the shallow trench isolation structure and the second sidewall height (vertical length of 400 between 510 and 390 in Fig. 74) is less than the height (vertical length of 320 and 440 in Fig. 74) of the shallow trench isolation structure.
Regarding claim 34, Kim further discloses the device of claim 30, wherein: each of the first fin spacers 369 (Fig. 74) and the second fin spacers 367 (Fig. 74) has a multilayer structure (see Fig. 74, wherein 369 and 367 formed on both sides of 405 and 400); and each of the first fin spacers 369 (Fig. 74) and the second fin spacers 367 (Fig. 74) includes silicon and nitrogen (“silicon nitride” in paragraph 0056).
Regarding claim 35, Kim in view of Lee discloses the device of claim 30, however Kim does not disclose adjacent first epitaxial source/drains merge together; and adjacent second epitaxial source/drains do not merge together.
Lee discloses adjacent first epitaxial source/drains 110 (Fig. 1B, paragraph 0017) merge together; and adjacent second epitaxial source/drains 150 (Fig. 1B, paragraph 0017) do not merge together.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form adjacent first epitaxial source/drains merge together; and adjacent second epitaxial source/drains do not merge together, as taught by Lee, since the epitaxial feature 110 (Lee, Fig. 1B, paragraph 0017) is tuned to improve device performance for a logic device, and the epitaxial feature 150 (Lee, Fig. 1B, paragraph 0017) is tuned to improve device performance for a memory device.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee as applied to claim 23 above, and further in view of Cheng et al. (US 2018/0247938) (hereafter Cheng).
Regarding claim 24, Kim in view of Lee discloses the semiconductor structure of claim 23, however Kim and Lee does not disclose the first semiconductor fin, the second semiconductor fin, the third semiconductor fin, and the fourth semiconductor fin have a germanium concentration that is less than about 50%.
Cheng discloses the first semiconductor fin (left 135 in Fig. 21, paragraph 0109), the second semiconductor fin (right 135 in Fig. 21, paragraph 0109), the third semiconductor fin (left 115 in Fig. 21, paragraph 0103), and the fourth semiconductor fin (right 115 in Fig. 21, paragraph 0103) have a germanium concentration (see paragraph 0109, wherein germanium concentration of 135 is in about 10 at. % to about 15 at. %; and see paragraph 0043, wherein 110 is silicon wafer such that germanium concentration of 115 which is part of 110 is 0) the that is less than about 50%.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim in view of Lee to form the first semiconductor fin, the second semiconductor fin, the third semiconductor fin, and the fourth semiconductor fin have a germanium concentration that is less than about 50%, as taught by Cheng, since when the difference in germanium concentration between the material compositions of fin layer 130 (Cheng, Fig. 21, paragraph 0090) and substrate 110 (Cheng, Fig. 21, paragraph 0090) is smaller (e.g. less than 15% Ge), substantially the same width can be formed for all fins, where fins with substantially the same width decreases the variability in properties of the later formed devices.
Claims 25-28 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee as applied to claim 21 above, and further in view of Shen et al. (US 2020/0161315) (hereafter Shen).
Regarding claim 25, Kim further discloses the semiconductor structure of claim 21, wherein each of the first semiconductor fin 306 (Fig. 73), the second semiconductor fin 308 (Fig. 73), the third semiconductor fin (left 302 in Fig. 73), and the fourth semiconductor fin (right 302 in Fig. 73) extend from a substrate 300 (Fig. 73); and the first semiconductor fin (region between second 320 and third 320 from the right corner of Fig. 74) and the second semiconductor fin (region between first 320 and second 320 from the right corner of Fig. 74) have a first fin height in the first source/drain region (“II” region in Fig. 74), the third semiconductor fin (region between second 320 and third 320 from the left corner of Fig. 74) and the fourth semiconductor fin (region between third 320 and fourth 320 from the left corner of Fig. 74) have a second fin height in the second source/drain region (“I” region in Fig. 74).
Kim and Lee do not disclose the second fin height is greater than the first fin height.
Shen discloses the second fin height (height of 110A in Fig. 10) is greater than the first fin height (height of 110B in Fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim in view of Lee to form the second fin height is greater than the first fin height, as taught by Lee, since first and second transistors 202, 204 (Shen, Fig. 10, paragraph 0038) may be any desired combination of transistor architectures designed to have different dimensions, shapes, etc.
Regarding claim 26, Kim further discloses the semiconductor structure of claim 25, further comprising an isolation structure (320 and 440 in Fig. 74) disposed over the substrate 300 (Fig. 74), wherein: the isolation structure (320 and 440 in Fig. 74) is disposed between the first semiconductor fin (region between second 320 and third 320 from the right corner of Fig. 74) and the second semiconductor fin (region between first 320 and second 320 from the right corner of Fig. 74), between the third semiconductor fin (region between second 320 and third 320 from the left corner of Fig. 74) and the fourth semiconductor fin (region between third 320 and fourth 320 from the right corner of Fig. 74), between the first epitaxial structure 425 (Fig. 74) and the second epitaxial structure 435 (Fig. 74), and between the third epitaxial structure (left 420 in Fig. 74) and the fourth epitaxial structure (right 420 in Fig. 74); and the isolation structure (320 and 440 in Fig. 74) has an isolation structure height (vertical length of 320 and 440 in Fig. 74), wherein the isolation structure height (vertical length of 320 and 440 in Fig. 74) is greater than the first fin height (vertical length of region between second 320 and third 320 from the right corner of Fig. 74) and the second fin height (vertical length of region between second 320 and third 320 from the left corner of Fig. 74).
Regarding claim 27, Kim further discloses the semiconductor structure of claim 25, wherein: the first semiconductor fin 306 (Fig. 73) and the second semiconductor fin 308 (Fig. 73) have a third fin height (vertical length of 306 in Fig. 73) in a first channel region 306 (Fig. 73), the third semiconductor fin (left 302 in Fig. 73) and the fourth semiconductor fin (right 302 in Fig. 73) have a fourth fin height (vertical length of 302 in Fig. 73) in a second channel region 302 (Fig. 73), the third fin height (vertical length of 306 in Fig. 73) is greater than the first fin height (vertical length of region between second 320 and third 320 from the right corner of Fig. 74), and the fourth fin height (vertical length of 302 in Fig. 73) is greater than the second fin height (vertical length of region between second 320 and third 320 from the left corner of Fig. 74); and
wherein the first channel region 306 (Fig. 73) forms another portion of the first device (“PMOS” of “II” region in Fig. 74) and the second source/drain region (“I” region in Fig. 74) forms another portion of the second device (“PMOS” of “I” region in Fig. 74).
Regarding claim 28, Kim further discloses the semiconductor structure of claim 27, wherein a ratio of the first spacer height H4 (Fig. 74) to the third fin height (vertical length of 306 in Fig. 73) is less than a ratio (see Fig. 74, wherein H4 is greater than H3; and see Fig. 73, wherein vertical lengths of 306 and 302 are same) of the second spacer height H3 (Fig. 74) to the fourth fin height (vertical length of 302 in Fig. 73).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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