Prosecution Insights
Last updated: August 17, 2026
Application No. 18/642,658

MANUFACTURING METHOD OF PACKAGE ON PACKAGE STRUCTURE

Non-Final OA §DP
Filed
Apr 22, 2024
Priority
Jun 29, 2018 — provisional 62/691,628 +3 more
Examiner
BELOUSOV, ALEXANDER
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
396 granted / 519 resolved
+8.3% vs TC avg
Strong +16% interview lift
Without
With
+16.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
22 currently pending
Career history
545
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
61.9%
+21.9% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 519 resolved cases

Office Action

§DP
DETAILED ACTION Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 3 and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10,535,644 (also, see claim 3 of the patent). Although the claims at issue are not identical, they are not patentably distinct from each other, as indicated below. A method, comprising: A manufacturing method of a package on package structure, comprising placing a lower package on a tape, wherein conductive bumps of the lower package are in contact with the tape; providing a first package on a tape carrier, wherein the first package comprises an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier; and bonding an upper package to the lower package mounting a second package on the first package through a plurality of electrical terminals by a thermo-compression bonding process wherein during the bonding, the conductive bumps are pressed against the tape so that a curvature of the respective conductive bump changes. which deforms the conductive bumps into a plurality of deformed conductive bumps, wherein each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion Regarding claim 3, Patent 10,535,644 claims wherein during the bonding, the respective conductive bump is deformed to a shape that comprises a base portion and a tip portion connected to the base portion and having a curvature different from a curvature of the base portion (claim 1). Regarding claim 4, Patent 10,535,644 claims wherein the curvature of the base portion of the respective conductive bump is smaller than the curvature of the tip portion of the respective conductive bump (claim 1). Allowable Subject Matter Claims 1-20 are considered allowable over prior art of record. The following is an examiner’s statement of reasons for allowance. Noting that claims 1, 3, and 4 are rejected under non-statutory double patenting as seen above. Because claims 1 is rejected, claims 2 and 5-10 are considered objected to, but would be allowable if written in independent form. The prior art of record, taken singly or in combination, does not disclose the totality of limitations of claims 1, 11 & 17, when taken in combination with the rest of the claim elements. To elaborate briefly on the above, this case is a CON of US-16/059,052 (and others). In the above case, the Applicant has received an Allowance, dated 12/24/2019. So, in the instant case, the Applicant basically took the allowable subject matter of the parent case, analyzed it and re-wrote it in 3 different independent claims and submitted the case as a CON. Examiner has performed some additional searching mostly using new CPC subclasses, keywords and various AI tools (see search history), but has not found any references that were better than the ones that were already cited in various parent cases (see Notice of References for best known references). The meat of the invention is that when one deposits a second package, on top of a first package, the resultant process done to upper package results in the lower package’s bumps being deformed by the tape carrier that lower package sits thereon. The best art was already discussed in various parent cases. The main failures of the best art are that (1) bump deforming happens NOT during/after placing of upper package on lower package and/or (2) bump deforming does not happen by the tape carrier on which lower package sits (typically, in the Prior Art, tape carrier is used for opposite purposes [Wingdings font/0xE0] to protect the bumps from deforming; see previous Allowances, for discussion of this). Hence, claims are indicated as allowable. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on Notice of References Cited, attached herewith. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Alexander Belousov/Patent Examiner, Art Unit 2894 07/11/26 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Apr 22, 2024
Application Filed
Jul 31, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707715
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
3y 6m to grant Granted Aug 11, 2026
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IMAGE SENSOR AND METHOD OF FABRICATING THE SAME
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Patent 12708042
SEMICONDUCTOR DEVICE WITH VOLUMETRICALLY-EXPANDED SIDE-CONNECTED INTERCONNECTS
2y 11m to grant Granted Aug 11, 2026
Patent 12701797
METHOD OF THINNING A SEMICONDUCTOR SUBSTRATE TO HIGH EVENNESS AND SEMICONDUCTOR SUBSTRATE HAVING A DEVICE LAYER OF HIGH EVENNESS
5y 1m to grant Granted Aug 04, 2026
Patent 12701798
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
3y 7m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
93%
With Interview (+16.5%)
2y 11m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 519 resolved cases by this examiner. Grant probability derived from career allowance rate.

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