Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-8 are pending and rejected. Claims 9-20 are withdrawn.
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-8 in the reply filed on 6/11/2026 is acknowledged. The traversal is on the ground(s) that there is no search burden. This is not found persuasive because the inventions require different fields of search requiring different search strategies and queries.
The requirement is still deemed proper and is therefore made FINAL.
Claims 9-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected inventions, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/5/2026.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 416, 916, 1002. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, US 4,886,765 in view of Takeyasu, US 5,637,534, Halpin, US 2012/0234230 A1, and Timans, US 2003/0183612 A1 and alternatively in view of Kuratomi, US 2020/0211852 A1.
Regarding claim 1, Chen teaches a material layer deposition method (depositing a metal film, Col. 2, lines 3-18). They teach using reactive ion etching to remove a TEOS layer (Col. 4, lines 3-21 and Fig. 1-2). They teach that the RIE is performed using etchants including carbon and fluorine (Col. 4, lines 22-52). They teach that polymeric contamination can be left on the surface of the wafers prior to metal deposition (Col. 5, lines 60-68 and Fig. 2). They teach that the contamination is primarily caused by the reactive ion etching step (Col. 6, lines 1-11). They teach heating the wafers at a temperature of about 800°C for about 20 minutes in an ambient consisting essentially of only dry oxygen is used to remove the contamination (Col. 6, lines 12-40). They teach that introducing 2% oxygen in the ambient during an anneal step at 950°C which just precedes the metal deposition step also aids in ensuring more complete removal of any residual polymeric contamination (Col. 6, lines 41-51).
Therefore, Chen provides a material layer deposition method comprising exposing an upper surface of the substrate to an etchant for etching the upper surface (TEOS layer Fig. 1-2) in a dry etching process (RIE), heating at least a portion of the upper surface to a predetermined temperature bake temperature to remove contaminants from the upper surface, and then after heating depositing a material layer onto the upper surface.
They do not teach supporting the substrate in an etching chamber and transferring the substrate to a deposition chamber.
Takeyasu teaches a semiconductor having a multilayered structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and a via hole (abstract). They teach manufacturing the device by a method that includes plasma etching at least one surface of the insulating interlayer to remove contaminates (abstract). They teach that a via plug is buried by using a film forming apparatus having an etching chamber, a CVD chamber, and a sputtering chamber (Col. 5, lines 26-30). They teach that the sample is provided in a load-lock chamber and then transferred to an etching chamber for RIE (Col. 5, lines 31-43). They teach that after etching the substrate is transferred to the CVD chamber via the transfer chamber (Col. 5, lines 56-62). They teach that once transferred to the CVD chamber, the substrate is heated in a hydrogen gas ambient and then undergoes a deposition process (Col. 5, line 63 to Col. 6, line 4). They teach that the heating in hydrogen is performed to reduce residual chlorine resulting from etching (Col. 11, lines 52-63 and Col. 12, line 27-55), indicating that the heating process is done in the deposition chamber.
From the teachings of Takeyasu, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have performed the RIE and deposition process using an apparatus similar to that of Takeyasu such that the substrate will be supported in a dry etch chamber for RIE and then transferred to the deposition chamber using a transfer chamber for heating/cleaning followed by deposition because Takeyasu teaches that such a process is suitable for etching, cleaning, and depositing a film on a substrate.
They do not teach that the surface is heated while the bulk material remains less than the upper surface.
Halpin teaches methods for low temperature, rapid baking to remove impurities form a semiconductor surface prior to in-situ deposition (abstract). They teach that a short, low temperature process is suitable for advanced, high density circuits with shallow junctions (abstract). They teach that silicon-fluorine and silicon-carbon bonds are often observed on the silicon substrate surface after cleaning, where fluorine and carbon contamination on the surface can be detrimental to the thermal budget and/or the quality of the layer to be grown or deposited on the surface of the substrate (0011). They teach loading the substrate onto a substrate support in a deposition chamber, providing an upper bank of substantially linear heat elements above the substrate support, providing power to the upper bank of heat elements to subject the substrate to a bake in a reducing environment for less than 45 seconds, stabilizing the substrate temperature after the bake; and depositing a layer by vapor deposition directly over the semiconductor region after stabilizing the temperature (0015 and Fig. 1). They teach using a plurality of radiant heat sources for heating (0032-0033 and Fig. 1). They teach that a plurality of sensors are positioned in proximity to the substrate, where the sensors include optical pyrometers (0042). They teach that based on the temperature sensors 28-31, the temperature controller can vary the power among the upper heat lamps to individually control the heating elements (0061-0062). They teach providing the low temperature bake first by purging in hydrogen and then quickly ramping up the temperature for less than about 45 seconds (0092-0094). They teach that the temperature controllers are set to 1100°C at full power, but that at full power the substrate generally stays in the 700-900°C range (0102). They teach that baking comprises raising the substrate temperature to greater than about 750°C and raising the substrate support temperature to less than about 750°C (claim 11). They teach that the process leaves very low levels of oxygen and carbon contamination at the surface (0095).
Timans teaches pulsed processing methods for heating objects such as semiconductor substrates with process control for multi-pulse processing of single substrate or of different substrates (abstract). They teach heating the substrate to a first temperature with a first heating source; deactivating or shutting off the power to the first heating source just before or when applying a first pulse of energy from a pulsed energy source to heat the device side surface of the substrate; and rapidly heating the first surface or device side of the substrate to a second temperature greater than the first surface or device side of the substrate to a second temperature greater than the first temperature by a first pulse of energy from a second heating source, where the second temperature may be an annealing temperature (0022). They teach that by deactivating the first heating source and heating the bulk of the substrate to the first temperature before or just when the pulse is applied from the pulse source the bulk of the wafer will remain at or near the first temperature and primarily only the first surface of the substrate will be heated rapidly to the second much higher temperature (0023). They teach that if the bulk temperature of the substrate creeps up, it can lead to undesired dopant diffusion and could cause subsequent applied pulses of equivalent energy to heat the front surface of the substrate to higher than desired temperature, or other unintended effects (0023). They teach using a closed-loop feedback control for the first heating source to help maintain the bulk of the substrate at or near the first temperature and well below the second treating or annealing temperature (0023). They teach that for annealing a silicon semiconductor wafer, the first temperature is preferably up to 1000°C or in the range of 200°C to 1100°C (0024). They teach that the second temperature is preferably in the range of 600°C to 1400°C (0024). They teach using heating sources such as lamps or lamp arrays for heating to the first temperature and irradiating the first surface using an arc lamp, a flash lamp, or a laser for pulse heating (0024-0025). They teach that when a series of pulses is used, the first pulse for a flash lamp or arc lamp has a duration of from 10 microseconds to 50 milliseconds (0029). They teach that the temperature of the front side of the substrate is measured by an optical sensor or a pyrometer or a series of optical sensors and/or pyrometers (0030). Therefore, Timans teaches using radiant heating sources in combination with pyrometers to control heating of a semiconductor wafer to heat the surface of the substrate to a higher temperature in pulsed heating while keeping the bulk temperature of the substrate below the surface temperature so as to prevent undesired dopant diffusion, overheat the surface, and other unintended effects.
From the teachings of Halpin and Timans, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have removed the etching contaminants using a rapid thermal baking or annealing process using radiant heating as provided by Halpin so as to heat the surface to a temperature for removing the contaminants while maintaining the bulk of the substrate below the surface temperature because Halpin teaches removing carbon and other impurities from a surface using rapid baking with radiant sources and Timans teaches that rapid thermal treating using radiant sources is desirable to heat the surface while maintaining the bulk of the substrate below the surface temperature to prevent undesired dopant diffusion, overheating of the surface, and other unintended effects such that it will be expected to remove the contaminants as desired while preventing the negative effects described by Timans. Therefore, at least a portion of the upper surface of the substrate will be heated to a predetermined upper surface bake temperature to remove contaminants from the upper surface resulting from etching while a bulk material temperature of a bulk material forming the substrate remains less than the predetermined upper surface bake temperature, wherein the heating is with a radiant heat source arranged above the deposition chamber.
As to measuring the electromagnetic radiation emitted from the upper surface, as noted above Halpin teaches using pyrometers to sense the temperature of the substrate (0042). They teach using a temperature controller that comprises independent PID controllers corresponding to the independent temperature sensors (0061). They teach that the temperature sensors comprise thermocouples which indirectly measure temperature (0061). They teach that based on the feedback from the heat elements 28-31, the temperature controller can vary the power among the upper heat lamps (0062). Therefore, Halpin teaches controlling the heaters based on the feedback from the temperature sensor, where the temperature sensors can be pyrometers.
Timans teaches that the temperature of the front side of the substrate is measured by a pyrometers or a series of pyrometers (0030). They teach determining the parameters of the pulse by providing a first test pulse of energy below the desired treating or annealing temperature (0031). They teach that during the test pulse, pulse energy data is collected by one or more optical sensors and/or substrate radiation is sensed by one or more pyrometers (0031). They teach that the pyrometer sense the emitted radiation from the front surface of the substrate, providing a means of tracking the front surface temperature (0031). They teach that the temperature rise of the front surface during the test pulse is used to determine the substrate absorptivity (0031). They teach that from the estimated absorptivity, pulse parameters (energy, duration, time between pulses) for a subsequent energy pulse are determined, and the next pulse is applied to heat the front side of the first surface to a desired treating or annealing temperature (0031).
From the teachings of Halpin and Timans, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have measured, with a pyrometer, electromagnetic radiation emitted from the upper surface and to have heated the surface based on the measurement with the pyrometer because Halpin teaches using a pyrometer for temperature sensing and using the measurement of temperature sensors to control the heating using the radiant sources and Timans teaches using pyrometers to sense radiation from an upper surface and using the measurement to determine the appropriate energy for the pulsed heating using radiant sources such that it will be expected to provide desirable control of the heating process.
Further, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have heated the substrate to a predetermined material layer deposition so as to provide a suitable temperature for the deposition, where since the predetermined temperature is not defined, any temperature is considered to meet the claimed requirements.
Alternatively: Kuratomi teaches methods for selectively depositing a titanium material layer atop a substrate having a silicon surface (abstract). They teach depositing the layer at a temperature of 200 to 800°C (0005). They teach that the wafer temperature is of about 425°C with a pedestal heated to about 450°C (0021).
From the teachings of Kuratomi, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have heated the substrate to 425°C for deposition of the titanium layer because Kuratomi teaches that such a temperature is desirable for depositing a titanium layer.
Regarding claim 3, Chen in view of Takeyasu, Halpin, and Timans and alternatively in view of Kuratomi suggests the process of claim 1. Chen teaches heating to about 800°C for about 20 minutes (Col. 6, lines 12-28). Halpin teaches heating during baking to greater than about 750°C (claim 11), where baking is done for less than 45 seconds (0015).
From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have optimized the temperature to be within the claimed range from the overlapping range of Halpin because Halpin teaches that such a range is desired for removing contaminants such that it will be expected to provide a suitable range for cleaning the substrate surface. According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” According to MPEP 2144.05 II A, “Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 4, Chen in view of Takeyasu, Halpin, and Timans and alternatively in view of Kuratomi suggest the process of claim 1. Chen teaches heating to about 800°C for about 20 minutes (Col. 6, lines 12-28). Halpin teaches heating during baking to greater than about 750°C (claim 11), where baking is done for less than 45 seconds (0015). Timans teaches heating to a second temperature in the range of 600-1400°C for 10 microseconds to 50 milliseconds (0024 and 0029).
From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have optimized the heating time to be within the claimed range from the overlapping range of Halpin and the range of Timans because Halpin indicates that such a time is suitable for removing contaminants from a surface and Timans suggests heating for a short time to prevent the bulk temperature from increasing such that it will be expected to heat the surface for contaminant removal while also preventing the bulk of the substrate from heating to the surface temperature. Further, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have optimize the heating time to be within the claimed range because they suggest providing the process to remove contaminants where Halpin teaches that heating can be used to remove contaminants using a time range overlapping the claimed range such that by optimizing the time to be within the claimed range it will be expected to also remove the contaminants prior to depositing the metal. According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.” According to MPEP 2144.05 II A, “Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 5, Chen in view of Takeyasu, Halpin, and Timans and alternatively in view of Kuratomi suggest the process of claim 1. Halpin further teaches using a plurality of radiant heat sources such that the radiant heat source comprises a plurality of heater elements or lamps which are individually controllable (0033, 0035, and Fig. 1). They teach using a temperature controller that comprises independent PID controllers corresponding to the independent temperature sensors (0061). They teach that the temperature sensors comprise thermocouples which indirectly measure temperature (0061). They teach that based on the feedback from the heat elements 28-31, the temperature controller can vary the power among the upper heat lamps (0062). Therefore, they teach measuring the temperature using sensors which are suggested to be pyrometers as noted above, and adjusting the temperature of the lamps using PID controllers.
Timans teaches sensing the emitted radiation from the front surface using a pyrometer to track the front surface temperature (0031). They teach that the temperature rise of the front surface during the test pulse is used to determine the substrate absorptivity (0031). They teach that from the estimated absorptivity, pulse parameters (energy, duration, time between pulses) for a subsequent energy pulse are determined, and the next pulse is applied to heat the front side of the first surface to a desired treating or annealing temperature (0031). Timans teaches that the heat sources are controlled by a computer/control arrangement which is configured for selectively applying an electrical power level to each of the background heating sources and pulsed heating sources to accomplish precise control (0071). Timans further teaches that pulsed heating is carried out with a series of pulses emitted by the pulsed heating source, where closed loop feedback control is applied to adjust the pulse parameters for each pulse applied to heat the front or device side of the substrate so as to not apply an energy pulse that will heat the front side to a temperature above the desired treating or annealing temperature (0030). They teach that the feedback is based upon measured substrate frontside temperature compared against a target or desired treating temperature (0095).
From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the plurality of heating elements and to have determined the upper surface temperature of the substrate based on the measuring of the pyrometer and adjust the electric power applied to the at least one heater element based on the measurement based on a comparison of the temperature with a predetermined temperature because Halpin teaches measuring the temperature using sensors which are suggested to be pyrometers as noted above, and adjusting the temperature of the lamps using PID controllers to provide the desired heating and Timans teaches tracking the temperature of the surface using the measured pyrometry information and adjusting the pulse parameters to provide the desired pulse parameters for heating, where the heating sources are provided with electric power, and where the closed-loop feedback includes comparing with a target value such that it will be expected to provide the required energy or power for the heating pulses.
Regarding claim 6, Chen in view of Takeyasu, Halpin, and Timans and alternatively in view of Kuratomi suggest the process of claim 5. Timans further teaches that pulsed heating is carried out with a series of pulses emitted by the pulsed heating source, where closed loop feedback control is applied to adjust the pulse parameters for each pulse applied to heat the front or device side of the substrate so as to not apply an energy pulse that will heat the front side to a temperature above the desired treating or annealing temperature (0030). They teach that the feedback is based upon measured substrate frontside temperature compared against a target or desired treating temperature (0095). From the teachings of Timans, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have repeated the determining of the upper surface temperature and the adjusting of the electric power to provide a closed-loop control over heating because Timans teaches that closed loop control allows for heating the surface to the desired temperature and not going over the temperature, where repeating the process will also be expected to ensure that the contaminants are removed.
Regarding claim 7, Chen in view of Takeyasu, Halpin, and Timans and alternatively in view of Kuratomi suggest the process of claim 1.
As noted above, Timans suggests using closed-loop control for the heating, where the measurement is compared against a target or desired treating temperature for determining the pulse parameters for heating the surface. Timans teaches that the heat sources are controlled by a computer/control arrangement which is configured for selectively applying an electrical power level to each of the background heating sources and pulsed heating sources to accomplish precise control (0071).
Halpin further teaches that the heat elements in the upper bank are also controlled such that more power is provided to the elements adjacent to the leading and trailing edges of the substrate to compensate for temperature variations along the direction of gas flow due to radiation cooling effects and on the leading and trailing edges of the substrate (0027). They teach that power is controlled to individual groups of the heat elements to provide additional heat to the edges of the substrate (0037). They teach that power to the various lamps can be controlled independently or in grouped zones in response to temperature sensors and PID controller (0037). They teach that the edges of the substrate can have additional heat losses because of the increased surface area at the substrate edge and from the heat sink effect from the cold support structures and adjacent areas of the reactor configuration (0037). They teach that to counteract the additional heat losses at the edges of the substrate, increased power can be supplied to the upper heat elements 13A, 13B above the edges of the substrate (0037 and Fig. 1).
From the teachings of Timans and Halpin, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have includes multiple radiant heat sources, including sources above the edges of the substrate and to have determined based on measurements from the pyrometer the temperature of the edge and other surface portions and to have adjusted the electric power applied to the heater elements based on a comparison of the measured temperature with a predetermined temperature because Timans teaches that such a comparison is desirable for determining the pulse parameters, where Timans indicates that electrical power is applied to the heating elements, and Halpin teaches using multiple heating elements for the different areas of the substrate, where the edge regions need more power due to heat losses such that it will be expected to more uniformly heat the surface of the substrate. Therefore, the upper surface will comprise a first portion and a second portion, i.e., the center regions and the edge regions, where the pyrometers will measure the various regions for determining the desired pulse parameters, including electric power, based on comparison with the target value so as to heat the surfaces as desired.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Takeyasu, Halpin, and Timans and alternatively in view of Kuratomi as applied to claim 1 above, and further in view of Ok, US 2023/0129619 A1.
Regarding claim 2, Chen in view of Takeyasu, Halpin, and Timans and alternatively in view of Kuratomi suggest the process of claim 1. Chen teaches forming integrated circuit devices and gate structures, including heavily doped region (Col. 1, lines 6-10, Col. 3, lines 27-41, Col. 4, lines 3-21, and Fig. 4).
They do not teach that the upper surface bake temperature is above a thermal budget temperature, and wherein electrical properties of patterned structures in the substrate are affected by the bulk material being above the thermal budget temperature.
Ok teaches a semiconductor structure for a phase change memory cell (abstract). They teach that a PCM device typically is fabricated during the back end of the line (BEOL) semiconductor manufacturing processes while transistors that may be present in the substrate are fabricated during the front end of the line (FEOL) manufacturing processes (0031). They teach that temperature sensitive elements of complementary metal oxide semiconductor (CMOS) logic circuits typically have a thermal budget for heat exposures to the gate stack and active dopant structures that is limited to annealing exposures at about 450°C for minutes, at about 500°C for seconds, and at about 950°C for hundreds of microseconds (0031). They teach that exceeding these thermal budgets thickens the gate dielectric, shifts transistor threshold voltages, and deactivates dopants (0031). They teach that the maximum thermal budget of BEOL processing should not exceed 400°C for conventional anneals and 1000°C for ultra-short scale anneals that are less than hundreds of microseconds (0031). They teach performing an annealing process to transform an enhancement material in contact with the phase change material into a metal silicide, where annealing can be a rapid anneal that does not exceed the thermal budget of the semiconductor device already present on the substrate (0039). They teach that the annealing process may be a millisecond anneal, such as a flash or laser anneal to provide a sufficient amount of heat to a layer to provide the desired effect without exceeding the thermal budget of either of the BEOL material set or the FEOL material set in a CMOS device (0084). They teach that forming the desired material requires temperature of about 500-700°C, where using short-scale anneals, high temperatures are provided without affecting transistors or the interconnect metals in the lower levels (0085).
From the teachings of Ok, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to provide the rapid annealing process such that removing the contaminant provides the heat required over the thermal budget over the lower elements in the structure while preventing BEOL patterned structures from being affected from the annealing process because Chen provides a gate structure in a semiconductor device for integrated circuits and Ok teaches that in circuits including gate structures, BEOL materials in transistors and such have electrical properties that are affected when the thermal budget is exceeded, where Ok indicates that shortening the annealing time while using a high temperature prevents damage to the materials such that the gate structures of Chen are expected to be included in devices that include patterned structures such as transistors in BEOL processes that will be affected by the heating and by using the rapid heating processes it will prevent damage to such structures.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Takeyasu, Halpin, and Timans and alternatively in view of Kuratomi as applied to claim 1 above, and further in view of Khosla, US 2012/0251271 A1.
Regarding claim 8, Chen in view of Takeyasu, Park, Halpin, and Timans suggest the process of claim 1.
They do not teach that the contaminants are from the transfer or prior to etchings.
Khosla teaches that substrate processing systems such as semiconductor processing systems are used to deposit film layers, metal layers or other types of layers on to substrates such as semiconductor wafers (0004). They teach that a substrate handling robot associated with a vacuum transfer chamber may be used to move the substrates from a load lock to one of the processing stations of the processing chamber (0005). They teach that the vacuum transfer chamber allows the transfer to be performed in a vacuum (0005). They teach that during transfers, it is desirable to avoid degradation of the film layers on the substrate, where degradation may occur when transferring the wafer through the vacuum transfer chamber to another one of the processing chamber (0006). They teach that oxidation of a metal layer may occur when transferring and that unwanted contamination such as hydrocarbons in the residual gases of the transfer chamber may also deposit onto the wafer during transport (0006).
From the teachings of Khosla, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have also removed contaminants resulting from the transferring process such as hydrocarbons because Khosla teaches that such contamination can occur during transfer such that it will be expected to clean the surface as desired.
Conclusion
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/CHRISTINA D MCCLURE/Examiner, Art Unit 1718
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