DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group II, species 3, claims 17-20 and new claims 21-36 in the reply filed on 7/20/26 is acknowledged.
Applicant’s cancellation of non-elected claims 1-16 is acknowledged.
Claims 17-36 are pending and subject to examination at this time.
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kirihara, US Patent No. 6747890 (e.g. Kirihara teaches in fig. 3 a memory comprising a read transistor, write transistor, storage node and capacitor.)
Allowable Subject Matter
Claims 29-36 are allowed.
Claims 26 and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al., US Publication No. 20240144994 A1 in view of Luk et al., US Publication No. 20050073871 A1 and Srinvasan et al., US Publication No 20080118731 A1.
Wu teaches:
17. A method of forming a gain cell random access memory cell, comprising (see figs. 1-4 and para. [0023] – [0025]):
forming a write transistor (WT), a first read transistor (RT2), and a second read transistor (RT1) on a substrate, wherein the write transistor is separated from the first read transistor and the second read transistor…;
forming a first wire level (e.g. wire level of CWBL, CRBL) over the substrate, the first wire level comprising a write bit line (e.g. wire of CWBL), a read bit line (e.g. wire of CRBL), and a plurality of interconnect wires, wherein the write bit line (e.g. wire of CWBL) is coupled to a first source/drain region (D1) of the write transistor (WT) and the read bit line (e.g. wire of CRBL) is coupled to a first source/drain region (D2) of the second read transistor (RT1);
forming a second wire level (e.g. wire level of SN) over the first wire level, the second wire level comprising a storage node (SN), wherein the storage node is coupled to a second source/drain region (S1) of the write transistor (WT) and a gate terminal (G3) of the first read transistor (RT2); and
forming a capacitor (e.g. capacitor C in fig. 1, para. [0025]) over the second wire level, the capacitor having a lower electrode coupled to the storage node (SN), a dielectric layer overlying the lower electrode, and an upper electrode over the dielectric layer (e.g. A lower electrode, dielectric layer and upper electrode forming a Metal-Insulator-Metal is inherent in a capacitor); and… See Wu at para. [0001] – [0027], figs. 1-4.
Regarding claim 17:
Wu does not expressly teach:
forming an isolation region in a substrate;
wherein the write transistor is separated from the first read transistor and the second read transistor by the isolation region;
In an analogous art, Luk teaches:
(see fig. 3A) forming an isolation region (STI) in a substrate (340);
wherein a write transistor (310) is separated from a read transistor (330) by the isolation region (STI); See Luk at para. [0070] – [0073].
It would have been obvious to one of ordinary skill in the art to modify Wu with Luk to form “the write transistor is separated from the first read transistor and the second read transistor by the isolation region” to physically and electrically separate adjacent transistors. See Luk at para. [0073]
Wu does not expressly teach the capacitor dielectric is a high-k dielectric and further:
performing a thermal anneal after forming the capacitor, the thermal anneal resulting in a material of the high-k dielectric layer transitioning into a highly- symmetrical crystalline phase.
In an analogous art, Srinivasan teaches:
(see fig. 2) forming a capacitor (12) over a second wire level (14), the capacitor having a lower electrode (16), a high-k dielectric layer (2) overlying the lower electrode, and an upper electrode (20) over the high-k dielectric layer; and
performing a thermal anneal after forming the capacitor (12), the thermal anneal resulting in a material of the high-k dielectric layer (2) transitioning into a highly- symmetrical crystalline phase, para. [0020] – [0023].
Wu further teaches:
18. The method of claim 17, wherein the first (RT2) and second (RT1) read transistors are formed sharing a source/drain region (Sc) in the substrate, figs. 3-4.
19. The method of claim 17, wherein the storage node (SN) is further formed coupled (e.g. by 100) to a gate terminal (G2) of the second read transistor (RT1), figs. 3-4, para. [0025].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wu with the teachings of Luk because the isolation region physically and electrically separates adjacent transistors. (e.g. Luk at para. [0073]).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wu with the teachings of Srinivasan because “Embodiments of the invention relate to forming a structure having a high dielectric constant (k) and a low leakage current. Specifically, embodiments of the invention relate to forming the structure having the high k and low leakage current from a perovskite-type material.” See Srinivasan at para. [0001].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Luk and Srinvasan, as applied to claim 17 above, in further view of Park, US 20100283091 A1.
Regarding claim 20:
Wu teaches all the limitations of claim 17 above, and further teaches:
20. The method of claim 17, further comprising: forming a third wire level (e.g. wire level of Cc) over the second wire level (e.g. wire level of SN) before forming the capacitor (e.g. capacitor C in fig. 1, para. [0025]), wherein the third wire level contacts a first via (Cc) extending between the third wire level and the storage node, and…
Wu does not expressly teach:
wherein the capacitor is formed contacting a second via extending between the third wire level and the lower electrode of the capacitor.
In an analogous art, Park teaches:
(see fig. 2) wherein the capacitor (100) is formed contacting a second via (SNC2) extending between a third wire level (LPC2) and the lower electrode of the capacitor (e.g. 17 is bottom plate of capacitor 100), para. [0088] – [0096].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wu with the teachings of Park because Park teaches or suggests the addition of vias/contacts allows the capacitor to be offset from bitlines to reduce parasitic capacitance. See Park at Abstract.
Claim(s) 21, 22 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al., US Publication No. 20240144994 A1 in view of Lee et al., US Publication No. 20140198560 A1
Wu teaches:
21. A method of forming a memory cell, comprising (see figs. 1-4 and para. [0023] – [0025]):
forming a write transistor (WR), a first read transistor (RT2), and a second read transistor (RT!) on a first side of a substrate, wherein the write transistor, the first read transistor, and the second read transistor extend across a first lateral area of the substrate;
forming a write bit line (e.g. of CWBL), a read bit line (e.g. of CRBL), and a storage node (SN) over the write transistor, wherein the write bit line (e.g. of CWBL) is coupled to a first source/drain region (D1) of the write transistor (WR), the read bit line (e.g. of CRBL) is coupled to a first source/drain region (D2) of the second read transistor (RT!), and wherein the storage node (SN) is coupled to a second source/drain region (S1) of the write transistor (WT) and a gate (G3) of the first read transistor (RT2); and
forming a capacitor (e.g. capacitor C in fig. 1, para. [0025]) over the storage node (SN), wherein the capacitor (C) is coupled (e.g.. by Cc) to the storage node (SN) … and wherein the capacitor (C) is vertically spaced from the storage node (SN) by a wire level (e.g. wire level of Cc) … See Wu at para. [0001] – [0027], figs. 1-4.
Regarding claim 21:
Wu does not expressly teach:
wherein the capacitor has a second lateral area that is less than the first lateral area.
In an analogous art, Lee teaches:
(see figs. 2-4) wherein a write transistor (310), a first read transistor (e.g. left 320), and a second read transistor (e.g. right 320) extend across a first lateral area of a substrate;
wherein a capacitor (330) has a second lateral area that is less than the first lateral area. See Lee at para. [0052] – [0073].
Regarding claim 22:
Wu does not expressly teach:
wherein a ratio of the second lateral area to the first lateral area is equal to or less than .8.
However, it would have been obvious to one of ordinary skill in the art to form “wherein a ratio of the second lateral area to the first lateral area is equal to or less than .8” because Lee teaches the capacitor (330) occupies less than half of the substrate area in fig. 3.
See also MPEP § 2125, Drawings as Prior Art:
” Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972)…When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). See MPEP § 2121.04 for more information on prior art drawings as “enabled disclosures.”
Regarding claim 28:
Lee further teaches:
28. The method of claim 21, wherein the first read transistor is an N- type transistor, and wherein the write transistor is a P-type transistor, para. [0012], para. [0119].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wu with the teachings of Lee because (i) “a size of the memory cell 300a may be reduced” (e.g. Lee at para. [0073]) and; (ii) “Therefore, the synchronization pulse signal SPS, which is applied to the lower electrode of the MOS capacitor 330 through the synchronization control line SCL, may be kept at an optimum or predetermined voltage Vopt between the supply voltage VDD and the ground voltage VSS in the wait mode. As a result, a sum of the leakage current flowing between the storage node SN and the body of the write transistor 310 may be reduced or minimized, and the leakage current flowing between the storage node SN and the body of the read transistor 325 may be reduced or minimized. As such, the data retention time of the memory cell 300b may increase.” (e.g. Lee at para. [0119])
Claim(s) 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Lee, as applied to claim 21 above, in further view of Sano et al., JP 2007081335 A.
Regarding claim 23:
Wu and Lee teach all the limitations of claim 1 above, and Wu further teaches:
wherein the first read transistor (RT2) and the second read transistor (RT1) are spaced in a first direction (e.g. horizontal) by a shared source/drain region (SC),
wherein the write transistor (WT) and the second read transistor (RT1) are spaced in a second direction (e.g. vertical) perpendicular to the first direction, figs. 3-4.
Wu does not expressly teach:
further comprising forming an isolation region within the substrate before forming the write transistor, the first read transistor, and the second read transistor, and wherein the write transistor and the second read transistor are spaced in a second direction perpendicular to the first direction by the isolation region.
In an analogous art, Sano teaches:
(see figs. 3, 6, 7, 62, 68 and 69) further comprising forming an isolation region (6 in fig. 7) within the substrate (7) before forming a write transistor (Qw) and a read transistor (Qr), and (see fig. 62) wherein the write transistor (Qw) and the read transistor (Qr) are spaced in a second direction (e.g. vertical) perpendicular to the first direction by the isolation region (6). See Sano at pages 9 and 40-44.
It would have been obvious to a person of ordinary skill in the art modify Wu with Sano to form “an isolation region within the substrate before forming the write transistor, the first read transistor, and the second read transistor, and wherein the write transistor and the second read transistor are spaced in a second direction perpendicular to the first direction by the isolation region” to provide element isolation. See Sano at page 14.
Regarding claim 24:
Wu teaches all the limitations of claim 21 above, and further teaches:
wherein the shared source/drain region (Sc) is spaced from the second source/drain region (S1) of the write transistor (WT), figs. 3-4.
Wu is silent regarding spaced from “…by the isolation region”.
However, one of ordinary skill in the art modifying Wu with Sano to form isolation region would form “wherein the shared source/drain region is spaced from the second source/drain region of the write transistor by the isolation region” because Sano’s figs. 7, 62, 68 and 29 shows the isolation region (6) vertically separates the read transistor (Qr) and the write transistor (Qw).
Wu is also silent wherein a gate of the second read transistor and a gate of the write transistor extend over the isolation region.
Sano further teaches wherein a gate (2G) of a read transistor (Qr) and a gate (1) of the write transistor (Qw) extend over the isolation region (6) in figs. 3, 6, 62, 68 and 69.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wu with the teachings of Sano in order to provide element isolation. See Sano at page 14.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Lee, as applied to claim 21 above, in further view of Moriya, JP 2002093924 A.
Regarding claim 25:
Wu and Lee teach all the limitations of claim 21 above, but do not expressly teach:
wherein the storage node has a first length in a first direction and a first width in a second direction different from the first direction, and wherein the capacitor has a second length in the first direction and a second width in the second direction that are respectively greater than the first length and the first width.
In an analogous art, Moriya teaches:
(see figs. 1-2 and 5) wherein the storage node (SN) has a first length in a first direction and a first width in a second direction different from the first direction, and wherein the capacitor (CAP) has a second length in the first direction and a second width in the second direction that are respectively greater than the first length and the first width. See Moriya at pages 2, 4 and 14-18.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wu with the teachings of Sano because the capacitor boosts the gate voltage. See Sano at pages 1-2.
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
23 September 2026
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