DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 06/12/2025 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because no English translation of the Taiwan Office Action has been provided. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Election/Restrictions
Applicant election of group I, reading on Claims 1-10, without traverse is acknowledged. Applicant has cancelled Claims 11-20, and added Claim 21-30, which read on group I as well. Claims 1-10 and 21-30 are examined on the merit.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 21-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “…(BEOL) layer disposed over …FEOL layer” in claims 1 and 21 is a relative term which renders the claim indefinite. The term “over” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In the instant case, flipping the orientation of the chip will result in same function performed by the device claimed in Claims 1 and 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1, 4-6, 8, 10, 21, 22, 24-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHARMA et al. (US 2023/0315331), (hereinafter, SHARMA).
RE Claim 1, 4, 21, 24 and 25, SHARMA discloses an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). The integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device. SHARMA discloses memory device comprising:
a front-end-of-line (FEOL) layer 110 and a back-end-of-line (BEOL) layer 120 disposed over the FEOL layer. Examiner notes that “front-end-of-line (FEOL) layer and a back-end-of-line (BEOL) layer” is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966; and
a plurality of content addressable memory (CAM) cells [abstract, 0073], each cell comprising a storage portion “memory” 190 and a compare portion “logic layer”. It is implicit that the comparison process is a “logical function”, hence meeting the claimed limitation,
wherein the storage portion of each cell of the plurality of CAM cells is disposed in the BEOL layer and the compare portion “logic” of each cell of the plurality of CAM cells is disposed in the FEOL layer.
Furthermore, SHARMA discloses memory device, wherein the compare “logic/selection” portion of each cell comprises a plurality of transistors “TFT” comprising “IGZO” oxide semiconductor “active region” channels [0034], hence meeting the limitations of Claims 4, 21 and 25.
Additionally, SHARMA discloses memory device,, wherein the compare portion and the storage portion are stacked to form a three-dimensional stack structure, which addresses Claim 24.
SHARMA does not disclose, wherein the storage portion of each cell of the plurality of CAM cells is disposed in the FEOL layer and the compare portion of each cell of the plurality of CAM cells is disposed in the BEOL layer.
However, rearrangement of parts is a prima facie obvious, absent unexpected results, particularly the storing, logic and comparing functions will be performed in the same manner, In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
RE Claims 5 and 27, SHARMA discloses memory device, wherein each transistor of the plurality of transistors further comprises a high-k gate dielectric [0024] and a metal gate electrode, such as copper [0034].
RE Claims 6 and 28, SHARMA discloses memory device, further comprising a plurality of conductive vias configured to connect the storage “memory” portion of each cell with the compare “logic” portion of each cell and electrically coupling storage “memory” portion and the compare “logic” portion [0030].
RE Claim 8 and 30, SHARMA disclose a memory device, wherein the plurality of CAM cells is configured to perform computing-in-memory (CIM) operations. Since “standalone” devices in that they are included in a chip that does not also include computing logic (e.g., transistors for performing processing operations) [0027], the claimed limitation is met.
RE Claim 10, SHARMA disclose an artificial intelligence system comprising the memory device of claim 1, wherein the plurality of CAM cells is configured to perform computing-in-memory (CIM) operations [0053].
RE Claim 22 and 26, SHARMA disclose a memory device, wherein the storage portion comprises a first plurality of transistors comprising a static random access memory (SRAM) cell, referring to FIG. 5 [0002, 0007, 0036 and 0042],
RE Claim 29, SHARMA disclose a memory device, wherein the plurality of CAM cells are arranged in an array and comparison results generated by the CAM cells are combined to perform a content search operation [0073].
Claim(s) 2, 3 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHARMA et al. (US 2023/0315331), (hereinafter, SHARMA) in view of Salahuddin et al. (US 2023/0206996), (hereinafter, Salahuddin).
RE Claim 2, SHARMA discloses memory device, wherein compare portion and the storage portion comprise a 3D stack;
the storage portion comprises a first plurality of transistors comprising a static random access memory (SRAM) cell, referring to FIG. 5 [0002, 0007, 0036 and 0042],
the compare “logic” portion comprises a second plurality of transistors,
wherein the plurality of transistors comprise a first channel material, which is inherently met;
wherein the second plurality of transistors comprise a second channel material, which is inherently met. It is the examiner position that up to the limitations as claimed of first and second channels do not imply they’re different;
SHARMA does not discloses memory device, wherein the second channel material comprises a material capable of being processed at a temperature that will not damage the first channel material.
However, in the same field of endeavor, Salahuddin discloses a multiport memory cell for register files, wherein the memory cell is partitioned to have a latching circuit and at least one write port located in the bottom tier and at least two read ports in the top tier. A word line trace for controlling the at least one write port is formed in the bottom tier metal layer stack and comprises two terminal sections and one intermediate section oriented perpendicularly to the terminal sections. The intermediate section is arranged between the pair of vias in a height direction of the memory cell. Salahuddin discloses a mid-bandgap gate work function materials can be used for the bottom tier active devices and large-bandgap gate work function materials for top tier active devices. Higher read speed, wherein using of mid-bandgap gate work function materials for the bottom tier active devices, which implies a different channel material of the top tier active devices, i.e. transistors, with a higher thermal budget is available for the processing of the top tier. This allows for improved performances of the top tier active devices [0016. 0051 and 0057].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to have the second channel material of SHARMA device having a material capable of being processed at a temperature that will not damage the first channel material, i.e. with a higher thermal budget similar to Salahuddin disclosed active device in order achieve improved performances of the different tiers active devices.
RE Claim 3, SHARMA discloses memory device, wherein active TFT layer, i.e. channel, comprises an oxide semiconductor material “IGZO” [0034].
SHARMA does not disclose memory device, wherein active TFT layer, i.e. channel, comprises silicon.
However, in the same field of endeavor, Salahuddin discloses a MOS device, wherein active layer of a transistor, i.e. channel of the SRAM device, comprises silicon.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to have SHARMA discloses memory device first and second transistors comprises silicon and oxide-semiconductor in order to achieve the desired improved performances of each different tiers of the device.
RE Claim 23, SHARMA does not explicitly disclose memory device, wherein the SRAM structure includes six transistors.
However, in the same field of endeavor, Salahuddin discloses a content-addressable memory wherein SRAM structure includes six transistors [0044].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use the SRAM architecture of SAHRMA with six transistors similar to Salahuddin disclosure in order to achieve optimize the memory architecture of SHARMA for high-density of bit cells and lowering power consumption [0045].
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHARMA et al. (US 2023/0315331), (hereinafter, SHARMA) in view of Gnoli et al. ("A skyrmion content-addressable cell for skyrmion magnetic memories," Nanotechnology, 22, 202203, 2022), (hereinafter, Gnoli).
RE Claim 7, SHARMA does not explicitly disclose memory device, wherein each cell of the plurality of CAM cells is connected to a match line configured to output the result of a logic operation.
However, Gnoli discloses ternary content-addressable memory cell based on skyrmion technology, wherein in CAM memories, every cell that belongs to a single word is connected to a match line that, connected to a sense amplifier [first pager, right-hand column, first paragraph], produces a match signal to show if a match for every single bit was found, hence meeting the claimed limitation that each cell of the plurality of CAM cells is connected to a match line configured to output the result of a logic operation.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to have SHARMA CAM perform functions in a similar way disclosed by Gnoli in order in order to extend its functionality.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHARMA et al. (US 2023/0315331), (hereinafter, SHARMA) in view of Liu et al. (“Analog content-addressable memory from complementary FeFETs,” Devices, Volume 2, Issue 2, 16, pages 1-11, February 2024), (hereinafter, Liu).
RE Claim 9, SHARMA does not disclose a memory device, wherein the CIM operations are configured to generate weighted output data and the plurality of CAM cells are figured to contribute weight values for the CIM operations.
However, in the same filed of endeavor, Liu discloses an analog content-addressable “ACAM” compute-in memory architecture based on complementary ferroelectric field effect transistors “FeFETs” and experimentally validating operation and function of each individual ACAM, wherein use ACAM for inference in a kernel regression machine was demonstrated such that Targets of input samples that are more similar to the test datum are up-weighted in the above summation [page 7, left-hand column, first paragraph], which implies CIM operations are configured to generate weighted output data and the plurality of CAM cells are figured to contribute weight values for the CIM operations, hence meeting the claimed limitation.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use similar memory architecture and operation of Liu’s disclosure for SHARMA’s memory in order to achieve high-throughput for massive search operations for neural network and artificial intelligence applications.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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