DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6-9, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by RYU et al. (US PG Pub 2022/0165736, hereinafter Ryu).
Regarding claim 1, figure 2 of Ryu discloses a semiconductor device, comprising:
a substrate (100);
a bit line structure (295) disposed over the substrate, wherein the bit line structure includes an insulating spacer structure (¶ 27) defining an air spacer (335); and
a sealing layer (470) disposed over the insulating spacer structure to cover the air spacer, wherein the sealing layer includes a carbon-containing material (¶ 103).
Regarding claim 2, figure 2 of Ryu discloses the insulating spacer structure includes a first spacer (305), a second spacer (335), and a third spacer (355), and wherein the second spacer defines the air spacer (¶ 27).
Regarding claim 6, figure 2 of Ryu discloses the sealing layer (470) contacts the bit line structure (295).
Regarding claim 7, figures 1 and 17 of Ryu disclose a landing pad (425) disposed over the bit line structure and having a recess region (430), wherein the sealing layer (470) is disposed in the recess region.
Regarding claim 8, figures 1 and 17 of Ryu disclose the sealing layer (440) is exposed to air in the recess region (430) and exposed to air in the air spacer (335).
Regarding claim 9, figures 1 and 17 of Ryu disclose the sealing layer (440) in the recess region (430) is partially etched (¶ 109).
Regarding claim 11, figure 2 of Ryu discloses the insulating spacer structure (¶ 27) is disposed between the bit line structure (295) and a storage node contact (425).
Note that figure 1 shows an array of repeating cell structures with storage node contacts.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by MUN et al. (US PG Pub 2024/0130109, hereinafter Mun).
Regarding claim 1, figure 6C of Mun discloses a semiconductor device, comprising:
a substrate (201);
a bit line structure (213) disposed over the substrate, wherein the bit line structure includes an insulating spacer structure (215U) defining an air spacer (AG); and
a sealing layer (AGC) disposed over the insulating spacer structure to cover the air spacer, wherein the sealing layer includes a carbon-containing material (¶ 241).
Regarding claim 2, figure 6C of Mun discloses the insulating spacer structure includes a first spacer (left part of 217), a second spacer (bottom of 217), and a third spacer (220), and wherein the second spacer defines the air spacer (¶ 27).
Regarding claim 3, figure 6C of Mun discloses the first spacer (217) and the third spacer (220) are connected.
Regarding claim 4, figure 6C of Mun discloses the first spacer (217) and the third spacer (220) include a nitrogen-containing material (¶ 174).
Regarding claim 5, figure 6C of Mun discloses the second spacer (bottom of 217) includes an oxygen-containing material (¶ 174), and the air spacer (AG) is defined over the oxygen-containing material.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817 1
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