Attorney’s Docket Number: TSMP20194040US01
Filing Date: 04/23/2024
Claimed Priority Date: 01/15/2021 (CON of 17/150,490 now PAT 11996317)
Applicant(s): Hsiao et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the application filed on 04/23/2024.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/643,212 filed on 04/23/2024 has been entered. Pending in this Office Action are claims 1-20.
Drawings
The drawings are objected to because, in Fig. 16B, the lead lines of references characters 38 and 34A seem to point to the wrong layers: 38 should point to the top/oxidized portion of Si layer 34, and 34A should point to the bottom/non-oxidized portion of Si layer 34 (e.g., similar to the depiction in Fig. 5B).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 10-16 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 10 recites the limitation “depositing a second liner in the first liner, wherein the second liner comprises silicon”, at L. 5. However, the application as originally filed is devoid of such manufacturing step. Instead, the application supports a step of depositing silicon layer 34 on oxide layer 32 (see, e.g., Fig. 3A and Par. [0016]). Accordingly, the claimed method step is directed to New Matter. In the interest on compact prosecution, the claim will be construed as reciting --depositing a second liner on the first liner, wherein the second liner comprises silicon--, as best understood by the examiner in view of the original disclosure, until further clarifications are provided by applicant.
The applicant may cancel the claim, amend the claim, or demonstrate explicit support for the claimed subject matter in the original disclosure (e.g., by citing specific excerpts from Specification or features in Drawings related to the claimed embodiment, as originally filed). A broad statement alleging support for the claimed subject matter will be considered non-persuasive.
Claims 11-16 depend from claim 10, thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US2019/0067027).
Regarding Claim 1, Wang (see, e.g., Figs. 2-12) shows all aspects of the instant invention, including a method comprising:
- etching a semiconductor substrate (e.g., semiconductor substrate 50) to form a trench (e.g., trench 61) and a semiconductor strip (e.g., strip/fin 64A or 64B), wherein a sidewall of the semiconductor strip is exposed to the trench (see, e.g., Figs. 2-4)
- depositing a silicon-containing layer (see, e.g., Par. [0034]: layer 86 of SiNx, SiON, or SiO2) on the semiconductor strip, wherein a sidewall portion of the silicon-containing layer is on the sidewall of the semiconductor strip (see, e.g., Fig. 6)
- filling the trench with a dielectric material (e.g., insulation material 62) (see, e.g., Fig. 7)
- performing a planarization process (see, e.g., Par. [0040]: CMP) to level a first top surface of the dielectric material (see, e.g., Fig. 8)
- after the planarization process, performing an oxidation process to oxidize the silicon-containing layer and to form a silicon oxide layer (see, e.g., Par. [0041]-[0046]: top layer 87 of dielectric layer 86 is oxidized and converted into an oxide of 86, e.g., silicon oxynitride) (see, e.g., Fig. 9)
- recessing the dielectric material (e.g., 62 recessed to surface 62U), wherein a portion of the semiconductor strip protrudes higher than a second top surface of the dielectric material and forms a semiconductor fin (e.g., portions of 64A/B having a height H3 above 62U) (see, e.g., Fig. 11)
Regarding Claim 8, Wang (see, e.g., Fig. 7) shows that the filling the dielectric material comprises:
- depositing the dielectric material as flowable (see, e.g., Par. [0037]: 62 comprises SiO2 and is formed by an FVCD process)
- before the planarization process, partially solidifying the dielectric material that is flowable (see, e.g., Par. [0039]: anneal process 420 may cure top portions of 62, while bottom portions may not be cured sufficiently)
Regarding Claim 17, Wang (see, e.g., Figs. 2-17) shows all aspects of the instant invention, including a method comprising:
- etching a semiconductor substrate (e.g., semiconductor substrate 50) to form a semiconductor strip (e.g., strip/fin 64A or 64B) (see, e.g., Figs. 2-4)
- depositing a silicon-containing liner (see, e.g., Fig. 5 and Par. [0028]: liner 83 of silicon; or Fig. 6 and Par. [0034]: layer 86 of SiNx, SiON, or SiO2) comprising:
a bottom portion on a top surface of the semiconductor substrate
a sidewall portion over and joined to the bottom portion
- depositing a dielectric material (e.g., insulation material 62) on the silicon-containing liner, wherein the dielectric material is flowable (see, e.g., Fig. 7 and Par. [0037]: 62 comprises SiO2 and is formed by an FVCD process)
- partially curing the dielectric material (see, e.g., Fig. 7 and Par. [0039]: anneal process 420 may cure top portions of 62, while bottom portions may not be cured sufficiently)
- polishing the dielectric material (see, e.g., Fig. 8 and Par. [0040]: CMP)
- performing an anneal process on the dielectric material (see, e.g., Fig. 9 and Par. [0041]-[0046]: anneal process 430 is performed to further cure remaining portions of 62)
- recessing the dielectric material (e.g., 62 recessed to surface 62U), wherein a portion of the semiconductor substrate between the recessed dielectric material forms a protruding semiconductor fin (e.g., portions of 64A/B having a height H3 above 62U) (see, e.g., Fig. 11)
- forming a gate dielectric (e.g., gate dielectric layer 96) on the protruding semiconductor fin (see, e.g., Figs. 16-17)
- forming a gate electrode (e.g., gate electrode 98) over the gate dielectric to form a transistor (see, e.g., Figs. 16-17).
Regarding Claim 18, Wang (see, e.g., Figs. 7-8) shows that at a first time after the dielectric material is partially cured, the bottom portion of the silicon-containing liner is a silicon layer (e.g., after 420, bottom portion of 83 is still a silicon layer).
Claims 1, 5-8, 10-13, 15-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (US2020/0135551).
Regarding Claim 1, Hsu (see, e.g., Figs. 1A-C and 2-8) shows all aspects of the instant invention, including a method comprising:
- etching a semiconductor substrate (e.g., semiconductor substrate 200) to form a trench (e.g., trench T) and a semiconductor strip (e.g., semiconductor fin 201), wherein a sidewall of the semiconductor strip is exposed to the trench (see, e.g., Figs. 2-3)
- depositing a silicon-containing layer on the semiconductor strip (e.g., liner layer 210 of Si), wherein a sidewall portion of the silicon-containing layer is on the sidewall of the semiconductor strip (see, e.g., Figs. 5A-B)
- filling the trench with a dielectric material (e.g., oxide layer 212) (see, e.g., Figs. 6A-6B)
- performing a planarization process to level a first top surface of the dielectric material (see, e.g., Figs. 7A-B and Par. [0024]: operation 110 wherein 212 is planarized by CMP)
- after the planarization process, performing an oxidation process to oxidize the silicon-containing layer and to form a silicon oxide layer (see, e.g., Par. [0026], L. 26-30: after planarization/CPM operation 110, non-oxidized layer 210B of Si liner 210 is converted into SiO2 by an additional wet or dry anneal)
- recessing the dielectric material, wherein a portion of the semiconductor strip protrudes higher than a second top surface of the dielectric material and forms a semiconductor fin (see, e.g., Figs. 8A-B and Par. [0025]-[0026]: top portion of 212 is etched so as to expose upper portion 201A of the semiconductor fins 201)
Regarding Claim 5, Hsu (see, e.g., Figs. 6-7) shows that the planarization process (e.g., planarization/CPM operation 110) results in a portion of the silicon-containing layer (e.g., 210) directly over the semiconductor fin to be removed.
Regarding Claim 6, Hsu (see, e.g., Fig. 4) shows that before the silicon-containing layer (e.g., 210) is deposited, depositing an additional silicon oxide layer (e.g., liner layer 208 of silicon oxide) in contact with the sidewall of the semiconductor strip.
Regarding Claim 7, Hsu (see, e.g., Figs. 5A-B) shows that the silicon-containing layer (e.g., 210) is in contact with the silicon oxide layer (e.g., 208).
Regarding Claim 8, Hsu (see, e.g., Figs. 6A-C and Par. [0018]-[0023]) shows that the filling the dielectric material comprises:
- depositing the dielectric material as flowable (see, e.g., Par. [0019]: 212 formed by flowable chemical vapor deposition (FCVD))
- before the planarization process, partially solidifying the dielectric material that is flowable (see, e.g., Par. [0022]: before planarization/CPM operation 110, performing UV curing operation 103 and/or dry annealing operation 105 to remove water from 212 and progressively transform 212 from flowable to solid silicon oxide material)
Regarding Claim 10, Hsu (see, e.g., Figs. 1A-C and 2-8) shows all aspects of the instant invention, including a method comprising:
- etching a semiconductor substrate (e.g., semiconductor substrate 200) to form a semiconductor strip (e.g., semiconductor fin 201) (see, e.g., Figs. 2-3)
- depositing a first liner (e.g., liner layer 208 of silicon oxide) on a sidewall and a top surface of the semiconductor strip, wherein the first liner comprises silicon oxide (see, e.g., Fig. 4)
- depositing a second liner (e.g., liner layer 210 of Si) on the first liner, wherein the second liner comprises silicon (see, e.g., Figs. 5A-B)
- depositing a dielectric material on the second liner (e.g., oxide layer 212), wherein a portion of the second liner is underlying the dielectric material (see, e.g., Figs. 6A-6B)
- curing the dielectric material to form an oxide region (see, e.g., Fig. 6C and Par. [0021]-[0022]: performing UV curing operation 103 and/or dry annealing operation 105 to remove water from 212 and progressively transform 212 from flowable to solid silicon oxide material)
- planarizing the oxide region, wherein a hard mask on top of the semiconductor strip is revealed (see, e.g., Fig. 7A-B and Par. [0024]: 212 is planarized by CMP, wherein the planarization process stops when mask layer 204 is exposed, such that mask layer 204 acts as the CMP stop layer in the planarization)
- converting at least a top portion of the second liner into a third liner that comprises an oxide (see, e.g., Fig. 6C and Par.[0021]-[0022]: surface portion 210A of Si liner 210 is converted into silicon oxide; and/or Fig. 8A-B and Par. [0026]: non-oxidized layer 210B of Si liner 210 is converted into SiO2).
Regarding Claim 11, Hsu (see, e.g., Fig. 7A-B and Par. [0024]) discloses that the planarization process stops when mask layer 204 is exposed, such that mask layer 204 acts as the CMP stop layer in the planarization. Therefore, Hsu shows that the planarizing the oxide region is stopped when the hard mask (e.g., 204) is revealed.
Regarding Claim 12, Hsu (see, e.g., Par. [0026]) discloses that after planarization/CPM operation 110, non-oxidized layer 210B of Si liner 210 is converted into SiO2 by an additional wet or dry anneal. Therefore, Hsu shows that the converting the second liner into the third liner is performed after the planarizing.
Regarding Claim 13, Hsu discloses that non-oxidized layer 210B of Si liner 210 overlaps semiconductor strip 201 and mask layer 204 (see, e.g., Figs. 6A-C and Par. [0021]); and that 212 is planarized by CMP, wherein the planarization process stops when mask layer 204 is exposed, such that mask layer 204 acts as the CMP stop layer in the planarization (see, e.g., Fig. 7A-B and Par. [0024]). Therefore, Hsu shows that the planarizing the oxide region (e.g., 212) is stopped after a top part of the second liner (e.g., 210B of 210) overlapping the semiconductor strip (e.g., 201) is removed.
Regarding Claim 15, Hsu (see, e.g., Figs. 2-3 and Par. [0013]-[0015]) discloses that fins 201 are patterned from a semiconductor substrate 200 of, e.g., silicon. Therefore, Hsu shows that a lower portion of the semiconductor strip (e.g., 201) is free from germanium.
Regarding Claim 16, Hsu (see, e.g., Par. [0017]) shows that the second liner (e.g., 210) has a thickness greater than about 0.5 nm (e.g., layer 210 has a thickness in a range substantially from 1 nm to 10 nm).
Regarding Claim 17, Hsu (see, e.g., Figs. 1A-C and 2-16) shows all aspects of the instant invention, including a method comprising:
- etching a semiconductor substrate (e.g., semiconductor substrate 200) to form a semiconductor strip (e.g., semiconductor fin 201) (see, e.g., Figs. 2-3)
- depositing a silicon-containing liner (see, e.g., Figs. 5A-B: liner layer 210 of Si) comprising:
a bottom portion on a top surface of the semiconductor substrate
a sidewall portion over and joined to the bottom portion
- depositing a dielectric material (e.g., oxide layer 212) on the silicon-containing liner, wherein the dielectric material is flowable (see, e.g., Fig. 6A-B and Par. [0019]: 212 formed by flowable chemical vapor deposition (FCVD))
- partially curing the dielectric material (see, e.g., Fig. 6C and Par. [0022]: performing UV curing operation 103 to remove water from 212 and progressively transform 212 from flowable to solid silicon oxide material)
- polishing the dielectric material (see, e.g., Fig. 7A-B and Par. [0024]: 212 is planarized by CMP)
- performing an anneal process on the dielectric material (see, e.g., Fig. 6C and Par. [0022]: performing dry annealing operation 105 to further remove water from 212)
- recessing the dielectric material, wherein a portion of the semiconductor substrate between the recessed dielectric material forms a protruding semiconductor fin (see, e.g., Figs. 8A-B and Par. [0025]-[0026]: top portion of 212 is etched so as to expose upper portion 201A of the semiconductor fins 201)
- forming a gate dielectric (e.g., gate dielectric 242) on the protruding semiconductor fin (see, e.g., Figs. 16A-B)
- forming a gate electrode (e.g., filling conductor 246) over the gate dielectric to form a transistor (see, e.g., Figs. 16A-B).
Regarding Claim 18, Hsu (see, e.g., Fig. 6C) shows that at a first time after the dielectric material is partially cured, the bottom portion of the silicon-containing liner is a silicon layer (e.g., after UV curing, bottom portion 210B of 210 is still a silicon layer).
Regarding Claim 20, Hsu (see, e.g., Figs. 8A-B and Par. [0026]) discloses that at operation 112, the second liner layer 210 is either already completely oxidized, or undergoes additional wet or dry anneal to convert the remaining second liner layer 210B of 210 into SiO2. Therefore, Hsu shows that at a second time after the transistor is formed (e.g., Figs. 16A-B), the bottom portion of the silicon-containing liner (e.g., 210B) has been converted as a silicon oxide layer.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2 and 6-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 and 6 of U.S. Patent No. 11,996,317.
Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent, and is a broader statement of the invention for which the patent was granted.
Claim 1 of patent No. 11,996,317 anticipates claim 1 of the instant invention.
Claim 1 of patent No. 11,996,317 anticipates claim 2 of the instant invention.
Claims 1 and 2 of patent No. 11,996,317 anticipate claim 6 of the instant invention.
Claims 1-3 of patent No. 11,996,317 anticipate claim 7 of the instant invention.
Claims 1 and 4 of patent No. 11,996,317 anticipate claim 8 of the instant invention.
Claims 1 and 6 of patent No. 11,996,317 anticipate claim 9 of the instant invention.
Allowable Subject Matter
Claims 3-4 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
Prosecution Insights