DETAILED ACTION
This action is responsive to the following communications: the Application filed April 23, 2024, and the information disclosure statement (IDS) filed April 23, 2024.
Claims 1-20 are pending. Claims 1, 10 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 23, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9-10, 16 and 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hong et al. (US 8,559,240) in view of Kim (US 2010/0149895).
Regarding independent claims 1 and 10, and its method independent claim 16, Hong et al. teach a sense amplifier for a memory device, the sense amplifier (see e.g., FIG. 1) comprising:
a primary latch (130) comprising a first set of transistors to latch a differential bitline voltage of a pair of bitlines in association with a memory operation; a
holding latch (110) comprising a second set of transistors to latch the differential bitline voltage of the pair of bitlines, wherein the second set of transistors have higher threshold voltages than the first set of transistors; and
control circuitry for independently controlling connectivity of the primary latch and the holding latch (see FIG. 2, i.e., a primary latch 130 (MN1, MP1, MN3 and MP3) gated (controlled) by LOUT/LOUTB; and holding latch 110 (MN1, MP1, MN2 and MP2) gated by LIN/LINB.
Hong et al. are silent with respect to the second set of transistors have higher threshold voltages than the first set of transistors.
However, Hong et al. disclose the CMOS latch-type sense amplifier circuit (claimed a primary latch) performs sensing operation fast (col. 2, lines 38-42).
Further, low threshold voltage MOS transistors, which enable fast operation, are a well-known technology in CMOS transistor characteristics.
For support, of the above asserted facts, see for example, Kim, para. 0046: … the local main-amp transistor can be composed of a low threshold MOS transistor, which achieves fast read operation …
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Kim to the teaching of Hong et al. such that two stage sense amplifier circuits, as taught by Hong et al., utilizes CMOS transistor characteristics such as low threshold voltage MOS transistors, which enable fast operation, as taught by Kim, for the purpose of achieving fast read operation for high speed applications (Kim, para. 0046), further these conventional technology are well established in the art of the semiconductor CMOS devices.
Further, regarding method claim 16, MPEP 2112.02(I) instructs examiners, “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
Regarding claim 9, Hong et al. and Kim, as combined, teach the limitations of claim 1.
Hong et al. further teach a column select circuit to couple or decouple the pair of bitlines with a corresponding pair of data lines (e.g., col. 3, lines 1-5: electrically connects or disconnects a bit line pair BL and BLB and the local input/output line pair LIO and LIOB by a column select line CSL …; further this is an inherent characteristic of memory devices).
Regarding claim 20, Hong et al. and Kim, as combined, teach the limitations of claim 16.
Hong et al. further teach deactivating the wordline; and performing a pre-charge cycle to equalize the pair of bitlines and reference nodes of the primary latch and the holding latch (FIG. 12 and accompanying disclosure).
Kim further teach deactivating the wordline; and performing a pre-charge (see e.g., para. 0053).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Kim for the same purpose of performing data read operations successively, further these claimed limitations are inherent characteristics of memory devices.
Allowable Subject Matter
Claims 2-8, 11-14 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825