DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of claim 18 “wherein the first gate, the second gate and the third gate are electrically connected to one another through a contact via” must be shown or the features canceled from the claim 18. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 8-16 and 19 are objected to because of the following informalities:
Claim 8 recites “the first via and second via” which should be replaced with
“the first via and the second via” for consistency with claim language.
Claim 9 recites “at least one of the transistors” (line 6) which should be replaced with
“at least one of transistors” to avoid antecedent basis issue because the limitation “the transistors” has not been explicitly recited in the claim.
Claim 16 recites “the first via and second via” which should be replaced with
“the first via and the second via” for consistency with claim language.
Claim 19 recites “the first via and second via” which should be replaced with
“the first via and the second via” for consistency with claim language.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,996,405 (hereinafter Patent’405) in view of US 2022/0199624 to Huang et al. (hereinafter Huang).
Claim 1 of Patent’405 recites a memory device (Col. 23, line 38), comprising:
a transistor (Col. 23, line 38), comprising:
gates (e.g., a first gate and a second gate) (Col. 23, lines 40-41) and channel layers (e.g., a first channel layer and a second channel layer) (Col. 23, lines 42-43; lines 48-49);
a source electrode and a drain electrode (Col. 23, lines 44-46 and lines 52-54) disposed at opposing sidewalls of each of the channel layers,
a first source electrode is electrically connected to a second source electrode through a first via (Col. 23, lines 55-56), and a first drain electrode is electrically connected to a second drain electrode through a second via (Col. 23, lines 57-58), and wherein the first via is positioned on a top surface of the first source electrode (Col. 23, lines 59-61), and the second via is positioned on a top surface of the first drain electrode (Col. 23, lines 61-63).
Claim 1 of Patent’405 does not specifically recites a stack of alternating gates and channel layers.
However, Huang teaches forming a transistor (e.g., a transistor stack structure 30) (Huang, Fig. 5A, ¶0053, ¶0037) comprising a stack of alternating gates (e.g., vertically stacked gate electrodes 110) (Huang, Fig. 5A, ¶0035, ¶0041-¶0043, ¶0053) and channel layers (e.g., channel layers 105), to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify claim 1 of Patent’405 by forming vertically stacked gate electrodes as taught by Huang to have a stack of alternating gates and channel layers, in order to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 of Patent’405 in view of US 2022/0199624 to Huang.
Claim 9 of Patent’405 recites a semiconductor die (Col. 24, line 45), comprising:
a semiconductor substrate (Col. 24, line 46);
an interconnect structure (Col. 24, lines 47-53) disposed over the semiconductor substrate, the interconnect structure comprising an embedded memory cell array, the embedded memory cell array comprising source lines, and memory devices, at least one of the memory devices comprising a transistor and a memory cell electrically connected to the transistor, and at least one of the transistors (Col. 24, lines 53-54) comprising:
a bottom gate (Col. 24, line 55);
a top gate disposed above the bottom gate (Col. 24, line 56);
a middle gate disposed between the bottom gate and the top gate (Col. 24, lines 57-58);
a first channel layer disposed between the bottom gate and the middle gate (Col. 24, lines 59-60);
a first source electrode and a first drain electrode disposed at opposite sidewalls of the first channel layer (Col. 24, lines 61-63);
a second channel layer disposed between the middle gate and the top gate (Col. 24, lines 64-65); and
a second source electrode and a second drain electrode disposed at opposite sidewalls of the second channel layer (Col. 25, lines 1-3),
wherein the first source electrode and the second source electrode are electrically connected to one of the source lines through a first via (Col. 25, lines 13-15), and the first drain electrode and the second drain electrode are electrically connected to the memory cell through a second via (Col. 25, lines 15-18), and wherein the first via penetrates the through second source electrode and lands on the first source electrode (Col. 25, lines 18-20), and the second via penetrates through the second drain electrode and lands on the first drain electrode (Col. 25, lines 20-22).
Claim 9 of Patent’405 does not specifically recites the first via vertically extends through the second source electrode and abuts the first source electrode, and the second via vertically extends through the second drain electrode and abuts the first drain electrode.
However, Huang teaches forming a transistor (e.g., a transistor stack structure 30) (Huang, Fig. 5A, ¶0053, ¶0037) comprising a stack of alternating gates (e.g., vertically stacked gate electrodes 110) (Huang, Fig. 5A, ¶0035, ¶0041-¶0043, ¶0053) and channel layers (e.g., channel layers 105), wherein the first via (581) vertically extends through the second source electrode (e.g., the upper source 106) and abuts the first source electrode (e.g., the lower source 106), to provide an improved three-dimensional array of memory cells with increased density and having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify claim 9 of Patent’405 by forming a first contact via and a second contact via vertically penetrating the upper source/drain electrode and abutting the lower source/drain electrode as taught by Huang to have the first via vertically extends through the second source electrode and abuts the first source electrode, and the second via vertically extends through the second drain electrode and abuts the first drain electrode, in order to provide an improved three-dimensional array of memory cells with increased density and having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of Patent’405 in view of US 2022/0199624 to Huang.
Claim 17 of Patent’405 recites a method, comprising:
forming a source electrode (e.g., first/second source electrode) (Col. 26, line 11) and a drain electrode (e.g., first/second drain electrode) (Col. 26, line 24);
forming a first via and a second via (Col. 26, line 36), a first source electrode is electrically connected to a second source electrode through the first via (Col. 26, lines 36-38), and a first drain electrode is electrically connected to a second drain electrode through the second via (Col. 26, lines 38-40), wherein the first via is positioned on a top surface of the first source electrode (Col. 26, lines 40-42), and the second via is positioned on a top surface of the first drain electrode (Col. 26, lines 43-45).
Claim 17 of Patent’405 does not specifically recites forming a stack of alternating gates and channel layers; forming a source electrode and a drain electrode at opposing sidewalls of each of the channel layers.
However, Huang teaches forming a transistor (e.g., a transistor stack structure 30) (Huang, Fig. 5A, ¶0053, ¶0037) comprising a stack of alternating gates (e.g., vertically stacked gate electrodes 110) (Huang, Fig. 5A, ¶0035, ¶0041-¶0043, ¶0053) and channel layers (e.g., channel layers 105), and forming a source electrode (106) and a drain electrode (106) at opposing sidewalls of each of the channel layers (e.g., lower and upper channel layers 105), to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify claim 17 of Patent’405 by forming vertically stacked gate electrodes as taught by Huang to have forming a stack of alternating gates and channel layers; forming a source electrode and a drain electrode at opposing sidewalls of each of the channel layers, in order to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0199624 to Huang in view of Ramaswamy (US 2019/0074277) and Park et al. (US 2011/0014754, hereinafter Park).
With respect to claim 1, Huang discloses a memory device (e.g., a memory array comprising double-sided cells 100 having transistor stack structures) (Huang, Figs. 1, 2A-2B, 5A-5B, ¶0026, ¶0029-¶0044, ¶0053-¶0054), comprising:
a transistor (e.g., a transistor stack structure 30) (Huang, Fig. 5A, ¶0053, ¶0037), comprising:
a stack of alternating gates (e.g., vertically stacked gate electrodes 110) (Huang, Fig. 5A, ¶0035, ¶0041-¶0043, ¶0053) and channel layers (e.g., channel layers 105);
a source electrode (e.g., 106) and a drain electrode (106) disposed at opposing sidewalls of each of the channel layers (105),
a first source electrode (e.g., one of the lower source/drain regions 106) (Huang, Fig. 5A, ¶0053, ¶0032-¶0033) is electrically connected (e.g., interconnect 581) (Huang, Fig. 5A, ¶0053) to a second source electrode (e.g., one of the upper source/drain regions 106) through a first via (581), and a first drain electrode (e.g., other one of the lower source/drain regions 106 on opposite sidewall of the lower channel layer 105) is under a second drain electrode (e.g., other one of the upper source/drain regions 106 on opposite sidewall of the upper channel layer 105), and wherein the first via (581) is positioned on a top surface of the first source electrode (e.g., one of the lower source/drain regions 106).
Further, Huang does not specifically disclose that a first drain electrode is electrically connected to a second drain electrode through a second via, wherein the second via is positioned on a top surface of the first drain electrode.
However, Ramaswamy teaches forming a memory array (Ramaswamy, Figs. 1-2, ¶0001-¶0006, ¶0035-¶0054) comprising memory cells including a capacitor electrode structure (52) (Ramaswamy, Figs. 1-2, ¶0041-¶0042) of the capacitors (34) having first electrodes (46) electrically connected to the lower first source/drain regions (20) and the upper first source/drain region (20) of the stacked transistor structures, wherein the capacitor electrode structure (52) extends through the stacked memory cells to electrically couple individual capacitors (34) of the memory cells to provide non-volatile memory with individually addressed memory cells. Further, the lower second source/drain regions (22) and the upper second source/drain region (22) are connected to the sense line (56) (Ramaswamy, Figs. 1-2, ¶0042-¶0043) extending through the stacked memory cells, wherein the sense line (56) is positioned on a top surface of the lower second source/drain region (22).
Further, Park teaches forming a memory device comprising stacked transistors (Park, Figs. 2, 9, ¶0006, ¶0030-¶0049, ¶0057-¶0074) with increased degree of integration, wherein transistors are arranged as thin film transistors, and a first drain region (9d) (Park, Fig. 2, ¶0045) of the lower transistor (TD1) is electrically connected to a second drain region (21d) of the upper transistor (TL1) through a second contact via (e.g., a contact metal pug 37 in Fig. 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory device of Huang by forming a capacitor electrode structure extending through the stacked memory cells and electrically connected to the first and second source/drain regions with the first electrodes of the individual capacitors as taught by Ramaswamy, and forming a contact plug/via to connect the source/drain electrodes of the staked transistors as taught by Park, wherein a second contact plug/via is disposed on a first drain electrode of the lower transistor and connected to a second drain electrode of the upper transistor as taught by Park to have the memory device, comprising: a first drain electrode is electrically connected to a second drain electrode through a second via, wherein the second via is positioned on a top surface of the first drain electrode, in order to provide improved non-volatile memory with individually addressed memory cells and having lager storage capacity with respect to an area occupied by a capacitor; and to provide improved memory device with increased degree of integration (Ramaswamy, ¶0001-¶0006, ¶0041-¶0043; Park, ¶0006, ¶0036-¶0037).
Regarding claim 2, Huang in view of Ramaswamy and Park discloses the memory device according to claim 1. Further, Huang discloses the memory device, wherein the stack of alternating gates and channel layers (110/105), comprises:
a first gate (e.g., a lower gate 110) (Huang, Fig. 5A, ¶0053, ¶0037);
a second gate (e.g., a middle gate110) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041) disposed above the first gate (110);
a first channel layer (e.g., a lower channel region 105) (Huang, Fig. 5A, ¶0053, ¶0030-¶0032) disposed between the first gate (e.g., the lower gate 110) and the second gate (e.g., the middle gate 110);
a third gate (e.g., an upper gate 110) (Huang, Fig. 5A, ¶0053, ¶0037) disposed above the second gate (e.g., the middle gate 110);
a second channel layer (e.g., an upper channel region 105) (Huang, Fig. 5A, ¶0053, ¶0030-¶0032) disposed between the second gate (e.g., the middle gate 110) and the third gate (e.g., the upper gate 110).
Further, Huang does not specifically disclose the memory device, wherein the top surface of the first source electrode substantially levels with the top surface of the first drain electrode and a top surface of the first channel layer, and a top surface of the second source electrode substantially levels with top surfaces of the second drain electrode and the second channel layer.
However, Park teaches forming the stacked transistors (Park, Figs. 2, 9, ¶0006, ¶0030-¶0049, ¶0057-¶0074) with increased degree of integration, wherein transistors are arranged as thin film transistors (TFT), wherein the stacked TFTs improve driving ability, and the top surface of the first source electrode (9s or 21s) substantially levels with the top surface of the first drain electrode (9d or 21d) and a top surface of the first channel layer, and a top surface of the second source electrode (21s or 33s) substantially levels with top surfaces of the second drain electrode (21d or 33d) and the second channel layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory device of Huang/Ramaswamy/Park by forming the stacked TFT transistors as taught by Park to have the memory device, wherein the top surface of the first source electrode substantially levels with the top surface of the first drain electrode and a top surface of the first channel layer, and a top surface of the second source electrode substantially levels with top surfaces of the second drain electrode and the second channel layer, in order to provide improved memory device including stacked TFTs to improve driving ability of transistors and to increase degree of integration (Park, ¶0006, ¶0036-¶0037).
Regarding claim 3, Huang in view of Ramaswamy and Park discloses the memory device according to claim 2. Further, Huang discloses the memory device, wherein the first channel layer (105, of the lower transistor) (Huang, Fig. 5A, ¶0053-¶0054), the first source electrode (106) and the first drain electrode (106) are located at a first level height while the second channel layer (105, of the upper transistor), the second source electrode and the second drain electrode are located at a second level height higher than the first level height, and the first gate (e.g., lower gate electrode 110, under the channel layer 105 of the lower transistor) is located at a level height lower than the first level height, the second gate (e.g., middle gate electrode 110) is located at a level height higher than the first level height and lower than the second level height, and the third gate (e.g., upper gate electrode 110) is located at a level height higher than the second level height.
Regarding claim 4, Huang in view of Ramaswamy and Park discloses the memory device according to claim 2. Further, Huang discloses the memory device, wherein the transistor further comprises a first gate (e.g., the lower gate 110) insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) disposed between the first gate (110) and the first channel layer (105), and the first gate is spaced apart from the first source electrode and the first drain electrode (e.g., the lower source/drain regions 106) by the first gate insulating layer.
Regarding claim 5, Huang in view of Ramaswamy and Park discloses the memory device according to claim 2. Further, Huang discloses the memory device, wherein the transistor further comprises a second gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) disposed between the second gate (e.g., the middle gate 110) and the first channel layer (105), and the second gate is spaced apart from the first source electrode and the first drain (e.g., the lower source/drain regions 106) by the second gate insulating layer.
Regarding claim 6, Huang in view of Ramaswamy and Park discloses the memory device according to claim 2. Further, Huang discloses the memory device, the transistor further comprises a third gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) disposed between the second gate (e.g., the middle gate 110) and the second channel layer (105), and the second gate is spaced apart from the second source electrode and the second drain electrode (e.g., the upper source/drain regions 106) by the third gate insulating layer.
Regarding claim 7, Huang in view of Ramaswamy and Park discloses the memory device according to claim 2. Further, Huang discloses the memory device, the transistor further comprises a fourth gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) disposed between the third gate (e.g., the upper gate 110) and the second channel layer, and the third gate is spaced apart from the second source electrode and the second drain electrode (e.g., the upper source/drain regions 106) by the fourth gate insulating layer.
Regarding claim 8, Huang in view of Ramaswamy and Park discloses the memory device according to claim 7. Further, Huang does not specifically disclose that the first via and second via further penetrates through the second gate insulating layer, the third gate insulating layer, and the fourth gate insulating layer.
Further, Ramaswamy teaches forming the capacitor electrode structure (52) (Ramaswamy, Figs. 1-2, ¶0041-¶0042) of the capacitors (34) having first electrodes (46) electrically connected to the lower first source/drain regions (20) and the upper first source/drain region (20) of the stacked transistor structures, and the sense line (56) (Ramaswamy, Figs. 1-2, ¶0042-¶0043) extend through the stacked memory cells including the second gate insulating layer (28) (Ramaswamy, Figs. 1-2, ¶0038), the third gate insulating layer (28), and the fourth gate insulating layer (28).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the memory device of Huang/Ramaswamy/Park by forming the plug/via and the second plug/via extending through the transistor stack as the capacitor electrode structure and the sense electrode extending through the stacked memory cells as taught by Ramaswamy to have the memory device, wherein the first via and second via further penetrates through the second gate insulating layer, the third gate insulating layer, and the fourth gate insulating layer, in order to provide improved non-volatile memory with individually addressed memory cells and having lager storage capacity with respect to an area occupied by a capacitor, and with increased levels of integration (Ramaswamy, ¶0001-¶0006, ¶0041-¶0043).
With respect to claim 17, Huang discloses a method (e.g., forming a memory array comprising double-sided cell structures 100) (Huang, Figs. 1, 2A-2B, 5A-5B, ¶0026, ¶0029-¶0044, ¶0053-¶0054), comprising:
forming a stack of alternating gates (e.g., vertically stacked gate electrodes 110) (Huang, Fig. 5A, ¶0035, ¶0041-¶0043, ¶0053) and channel layers (e.g., channel layers 105);
forming a source electrode (e.g., 106) and a drain electrode (106) at opposing sidewalls of each of the channel layers (105),
forming a first via (581), a first source electrode (e.g., one of the lower source/drain regions 106) (Huang, Fig. 5A, ¶0053, ¶0032-¶0033) is electrically connected (e.g., interconnect 581) (Huang, Fig. 5A, ¶0053) to a second source electrode (e.g., one of the upper source/drain regions 106) through the first via (581), and a first drain electrode (e.g., other one of the lower source/drain regions 106 on opposite sidewall of the lower channel layer 105) is under a second drain electrode (e.g., other one of the upper source/drain regions 106 on opposite sidewall of the upper channel layer 105), wherein the first via (581) is positioned on a top surface of the first source electrode (e.g., one of the lower source/drain regions 106).
Further, Huang does not specifically disclose forming a second via, a first drain electrode is electrically connected to a second drain electrode through the second via, wherein the second via is positioned on a top surface of the first drain electrode.
However, Ramaswamy teaches forming a memory array (Ramaswamy, Figs. 1-2, ¶0001-¶0006, ¶0035-¶0054) comprising memory cells including a capacitor electrode structure (52) (Ramaswamy, Figs. 1-2, ¶0041-¶0042) of the capacitors (34) having first electrodes (46) electrically connected to the lower first source/drain regions (20) and the upper first source/drain region (20) of the stacked transistor structures, wherein the capacitor electrode structure (52) extends through the stacked memory cells to electrically couple individual capacitors (34) of the memory cells to provide non-volatile memory with individually addressed memory cells. Further, the lower second source/drain regions (22) and the upper second source/drain region (22) are connected to the sense line (56) (Ramaswamy, Figs. 1-2, ¶0042-¶0043) extending through the stacked memory cells, wherein the sense line (56) is positioned on a top surface of the lower second source/drain region (22).
Further, Park teaches forming a memory device comprising stacked transistors (Park, Figs. 2, 9, ¶0006, ¶0030-¶0049, ¶0057-¶0074) with increased degree of integration, wherein transistors are arranged as thin film transistors, and a first drain region (9d) (Park, Fig. 2, ¶0045) of the lower transistor (TD1) is electrically connected to a second drain region (21d) of the upper transistor (TL1) through a second contact via (e.g., a contact metal pug 37 in Fig. 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Huang by forming a capacitor electrode structure extending through the stacked memory cells and electrically connected to the first and second source/drain regions with the first electrodes of the individual capacitors as taught by Ramaswamy, and forming a contact plug/via to connect the source/drain electrodes of the staked transistors as taught by Park, wherein a second contact plug/via is disposed on a first drain electrode of the lower transistor and connected to a second drain electrode of the upper transistor as taught by Park to have the method, comprising: forming a second via, a first drain electrode is electrically connected to a second drain electrode through the second via, wherein the second via is positioned on a top surface of the first drain electrode, in order to provide improved non-volatile memory with individually addressed memory cells and having lager storage capacity with respect to an area occupied by a capacitor; and to provide improved memory device with increased degree of integration (Ramaswamy, ¶0001-¶0006, ¶0041-¶0043; Park, ¶0006, ¶0036-¶0037).
Regarding claim 20, Huang in view of Ramaswamy and Park discloses the method according to claim 17. Further, Huang discloses the method further comprising: forming a memory cell (e.g., a capacitor 171/172) (Huang, Fig. 5A, ¶0053, ¶0036-¶0037) over electrically connected to the first drain electrode (e.g., the drain of the upper transistor) and second drain electrode (e.g., the drain of the lower transistor).
Claims 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0411426 to Lajoie et al. (hereinafter Lajoie) in view of Huang (US 2022/0199624), Ramaswamy (US 2019/0074277), and Park (US 2011/0014754).
With respect to claim 9, Lajoie discloses a semiconductor die (e.g., a memory device comprising memory cells including a thin film transistor and a capacitor in the metallization layer on a semiconductor substrate) (Lajoie, Figs. 2, 4, ¶0001, ¶0024-¶0032, ¶0042-¶0046, ¶0056-¶0061), comprising:
a semiconductor substrate (e.g., silicon or silicon-on-insulator substrate 251) (Lajoie, Figs. 2, 4, ¶0001, ¶0024, ¶0043);
an interconnect structure (240) (Lajoie, Figs. 2, 4, ¶0043, ¶0046) disposed over the semiconductor substrate (251), the interconnect structure (240) comprising an embedded memory cell array (e.g., 200 in Fig. 2 or 402, 404, 406, and 408 in Fig. 4) (Lajoie, Figs. 2, 4, ¶0042, ¶0043-¶0045, ¶0056-¶0061), the embedded memory cell array comprising source lines (e.g., S1 and S2), and memory devices (e.g. a thin film transistor 414 and a storage cell 412 including a capacitor), at least one of the memory devices comprising a transistor (414) and a memory cell (e.g., 412) electrically connected to the transistor (e.g., the drain 213 in Fig. 2 or 407 in Fig. 4 is connected to the capacitor), and at least one of the transistors (414) comprising:
a gate (205) (Lajoie, Figs. 2, 4, ¶0043, ¶0045, ¶0056-¶0059);
a first channel layer (209);
a first source electrode (211) and a first drain electrode (213 in Fig. 2 or 407 in Fig. 4) disposed at opposite sides of the first channel layer (209), wherein the first source electrode (e.g., 211 in Fig. 2 or 409 in Fig. 4) is electrically connected to one of the source lines (S1/S2), and the first drain electrode (e.g., 213 in Fig. 2 or 407 in Fig. 4) is electrically connected to the memory cell (e.g., capacitor 220 in Fig. 2).
Further, Lajoie does not specifically disclose (1) a bottom gate; a top gate disposed above the bottom gate; a middle gate disposed between the bottom gate and the top gate; a first channel layer disposed between the bottom gate and the middle gate; a second channel layer disposed between the middle gate and the top gate; and a second source electrode and a second drain electrode disposed at opposite sides of the second channel layer, wherein the first source electrode and the second source electrode are electrically connected to one of the source lines through a first via, (2) wherein the first drain electrode and the second drain electrode are electrically connected to the memory cell through a second via, and wherein the first via vertically extends through the second source electrode and abuts the first source electrode, and the second via vertically extends through the second drain electrode and abuts the first drain electrode.
Regarding (1) and (2), Huang discloses a memory device (e.g., a memory array comprising double-sided cell structures 100) (Huang, Figs. 1, 2A-2B, 5A-5B, ¶0026, ¶0029-¶0044, ¶0053-¶0054) comprising: a transistor (e.g., a transistor stack structure 30) (Huang, Fig. 5A, ¶0053, ¶0037) and a capacitor (171/172). The transistor comprises a bottom gate (e.g., a lower gate 110) (Huang, Fig. 5A, ¶0053, ¶0037) and a middle gate (e.g., a middle gate 110) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041) disposed above the bottom gate (110), a first channel layer (e.g., a lower channel region 105) (Huang, Fig. 5A, ¶0053, ¶0030-¶0032) disposed between the bottom gate (e.g., the lower gate 110) and the middle gate (e.g., the middle gate 110), a first source electrode (e.g., one of the lower source/drain regions 106) (Huang, Fig. 5A, ¶0053, ¶0032-¶0033) and a first drain electrode (e.g., one of the lower source/drain regions 106) disposed at opposite sides of the first channel layer (105), a top gate (e.g., an upper gate 110) (Huang, Fig. 5A, ¶0053, ¶0037) disposed above the middle gate (e.g., the middle gate 110), wherein the top gate is electrically connected to the bottom gate and the middle gate (e.g., a common gate electrode 110), a second channel layer (e.g., an upper channel region 105) (Huang, Fig. 5A, ¶0053, ¶0030-¶0032) disposed between the middle gate (e.g., the middle gate 110) and the top gate (e.g., the upper gate 110), a second source electrode (e.g., one of the upper source/drain regions 106) and a second drain electrode (e.g., one of the upper source/drain region 106) disposed at opposite sides of the second channel layer (105), wherein the first source electrode (e.g., one of the lower source/drain regions 106) is electrically connected (e.g., interconnect 581) (Huang, Fig. 5A, ¶0053) to the second source electrode (e.g., one of the upper source/drain regions 106) through a first via (581), wherein the memory cell (e.g., a capacitor 171/172) (Huang, Fig. 5A, ¶0053, ¶0036-¶0037) is electrically connected to the second drain electrode (e.g., one of the upper source/drain regions 106) through a second via/plug (161), wherein the first via (581) vertically extends through the second source electrode (e.g., the upper source 106) and abuts the first source electrode (e.g., the lower source 106).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the semiconductor die of Lajoie by forming a memory cell as a double -sided memory cell including a stacked transistor structure as taught by Huang, wherein the first source electrode and the second source electrode are electrically connected to one of the source lines of Lajoie to have at least one of the transistors comprising: a bottom gate; a top gate disposed above the bottom gate; a middle gate disposed between the bottom gate and the top gate; a first channel layer disposed between the bottom gate and the middle gate; a second channel layer disposed between the middle gate and the top gate; and a second source electrode and a second drain electrode disposed at opposite sides of the second channel layer, wherein the first source electrode and the second source electrode are electrically connected to one of the source lines through a first via, wherein the second drain electrode is electrically connected to the memory cell through a second via, and wherein the first via vertically extends through the second source electrode and abuts the first source electrode, in order to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
Regarding (2), Ramaswamy teaches forming a memory array (Ramaswamy, Figs. 1-2, ¶0001-¶0006, ¶0035-¶0054) comprising memory cells including a capacitor electrode structure (52) (Ramaswamy, Figs. 1-2, ¶0041-¶0042) of the capacitors (34) having first electrodes (46) electrically connected to the lower first source/drain regions (20) and the upper first source/drain region (20) of the stacked transistor structures, wherein the capacitor electrode structure (52) extends through the stacked memory cells to electrically couple individual capacitors (34) of the memory cells to provide non-volatile memory with individually addressed memory cells.
Further, Park teaches forming a memory device comprising stacked transistors (Park, Figs. 2, 9, ¶0006, ¶0030-¶0049, ¶0057-¶0074) with increased degree of integration, wherein transistors are arranged as thin film transistors, and a first drain region (9d) (Park, Fig. 2, ¶0045) of the lower transistor (TD1) is electrically connected to a second drain region (21d) of the upper transistor (TL1) through a second contact via (e.g., a contact metal pug 37 in Fig. 2), and the second via vertically extends through the second drain electrode (22d) and abuts the first drain electrode (9d).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor die of Lajoie/Huang by forming a capacitor electrode structure extending through the stacked memory cells and electrically connected to the first and second source/drain regions with the first electrodes of the individual capacitors as taught by Ramaswamy, and forming a contact plug/via to connect the source/drain electrodes of the staked transistors as taught by Park, wherein a second contact plug/via vertically extends through the second drain electrode of the upper transistor and directly connected to the first drain electrode of the lower transistor as taught by Park to have the semiconductor die, wherein the first drain electrode and the second drain electrode are electrically connected to the memory cell through a second via, and wherein the second via vertically extends through the second drain electrode and abuts the first drain electrode, in order to provide improved non-volatile memory with individually addressed memory cells and having lager storage capacity with respect to an area occupied by a capacitor; and to provide improved memory device with increased degree of integration (Ramaswamy, ¶0001-¶0006, ¶0041-¶0043; Park, ¶0006, ¶0036-¶0037)
Regarding claim 10, Lajoie in view of Huang, Ramaswamy, and Park discloses the semiconductor die according to claim 9. Further, Lajoie does not specifically disclose the semiconductor die, wherein a top surface of the first source electrode substantially levels with top surfaces of the first drain electrode and the first channel layer, and a top surface of the second source electrode substantially levels with top surfaces of the second drain electrode and the second channel layer.
However, Park teaches forming the stacked transistors (Park, Figs. 2, 9, ¶0006, ¶0030-¶0049, ¶0057-¶0074) with increased degree of integration, wherein transistors are arranged as thin film transistors (TFT), wherein the stacked TFTs improve driving ability, and the top surface of the first source electrode (9s or 21s) substantially levels with the top surface of the first drain electrode (9d or 21d) and a top surface of the first channel layer, and a top surface of the second source electrode (21s or 33s) substantially levels with top surfaces of the second drain electrode (21d or 33d) and the second channel layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor die of Lajoie/Huang/Ramaswamy/Park by forming the stacked TFT transistors as taught by Park to have the semiconductor die, wherein a top surface of the first source electrode substantially levels with top surfaces of the first drain electrode and the first channel layer, and a top surface of the second source electrode substantially levels with top surfaces of the second drain electrode and the second channel layer, in order to provide improved memory device including stacked TFTs to improve driving ability of transistors and to increase degree of integration (Park, ¶0006, ¶0036-¶0037).
Regarding claim 11, Lajoie in view of Huang, Ramaswamy, and Park discloses the semiconductor die according to claim 10. Further, Lajoie does not specifically disclose the memory device, wherein the first channel layer, the first source electrode and the first drain electrode are located at a first level height while the second channel layer, the second source electrode and the second drain electrode are located at a second level height higher than the first level height, and the bottom gate is located at a level height lower than the first level height, the middle gate is located at a level height higher than the first level height and lower than the second level height, and the top gate is located at a level height higher than the second level height.
However, Huang discloses the memory device, wherein the first channel layer (105, of the lower transistor) (Huang, Fig. 5A, ¶0053-¶0054), the first source electrode (106) and the first drain electrode (106) are located at a first level height while the second channel layer (105, of the upper transistor), the second source electrode and the second drain electrode are located at a second level height higher than the first level height, and the bottom gate (e.g., lower gate electrode 110, under the channel layer 105 of the lower transistor) is located at a level height lower than the first level height, the middle gate (e.g., middle gate electrode 110) is located at a level height higher than the first level height and lower than the second level height, and the top gate (e.g., upper gate electrode 110) is located at a level height higher than the second level height.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the semiconductor die of Lajoie/Huang/Ramaswamy /Park by forming a memory cell as a double -sided memory cell including a stacked transistor structure as taught by Huang to have the semiconductor die, wherein the first channel layer, the first source electrode and the first drain electrode are located at a first level height while the second channel layer, the second source electrode and the second drain electrode are located at a second level height higher than the first level height, and the bottom gate is located at a level height lower than the first level height, the middle gate is located at a level height higher than the first level height and lower than the second level height, and the top gate is located at a level height higher than the second level height, in order to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
Regarding claim 12, Lajoie in view of Huang, Ramaswamy, and Park discloses the semiconductor die according to claim 9. Further, Lajoie does not specifically disclose the semiconductor die, wherein the at least one of the transistors further comprises a first gate insulating layer disposed between the bottom gate and the first channel layer, and the bottom gate is spaced apart from the first source electrode and the first drain electrode by the first gate insulating layer.
However, Huang discloses the memory device, wherein the transistor further comprises a first gate (e.g., the lower gate 110) insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) disposed between the first gate (110) and the first channel layer (105), and the first gate is spaced apart from the first source electrode and the first drain electrode (e.g., the lower source/drain regions 106) by the first gate insulating layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the semiconductor die of Lajoie/Huang/Ramaswamy/ Park by forming a memory cell as a double -sided memory cell including a stacked transistor structure as taught by Huang to have the semiconductor die, wherein the at least one of the transistors further comprises a first gate insulating layer disposed between the bottom gate and the first channel layer, and the bottom gate is spaced apart from the first source electrode and the first drain electrode by the first gate insulating layer, in order to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
Regarding claim 13, Lajoie in view of Huang, Ramaswamy, and Park discloses t the semiconductor die according to claim 9. Further, Lajoie does not specifically disclose the semiconductor die, wherein the at least one of the transistors further comprises a second gate insulating layer disposed between the middle gate and the first channel layer, and the middle gate is spaced apart from the first source electrode and the first drain electrode by the second gate insulating layer.
However, Huang discloses the memory device, wherein the transistor further comprises a second gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) disposed between the second gate (e.g., the middle gate 110) and the first channel layer (105), and the second gate is spaced apart from the first source electrode and the first drain (e.g., the lower source/drain regions 106) by the second gate insulating layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the semiconductor die of Lajoie/Huang/Ramaswamy/ Park by forming a memory cell as a double -sided memory cell including a stacked transistor structure as taught by Huang to have the semiconductor die, wherein the at least one of the transistors further comprises a second gate insulating layer disposed between the middle gate and the first channel layer, and the middle gate is spaced apart from the first source electrode and the first drain electrode by the second gate insulating layer, in order to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
Regarding claim 14, Lajoie in view of Huang, Ramaswamy, and Park discloses the semiconductor die according to claim 9. Further, Lajoie does not specifically disclose t the semiconductor die, wherein the at least one of the transistors further comprises a third gate insulating layer disposed between the middle gate and the second channel layer, and the middle gate is spaced apart from the second source electrode and the second drain electrode by the third gate insulating layer.
However, Huang discloses the memory device, the transistor further comprises a third gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) disposed between the second gate (e.g., the middle gate 110) and the second channel layer (105), and the second gate is spaced apart from the second source electrode and the second drain electrode (e.g., the upper source/drain regions 106) by the third gate insulating layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the semiconductor die of Lajoie/Huang/Ramaswamy/ Park by forming a memory cell as a double -sided memory cell including a stacked transistor structure as taught by Huang to have the semiconductor die, wherein the at least one of the transistors further comprises a third gate insulating layer disposed between the middle gate and the second channel layer, and the middle gate is spaced apart from the second source electrode and the second drain electrode by the third gate insulating layer, in order to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
Regarding claim 15, Lajoie in view of Huang, Ramaswamy, and Park discloses the semiconductor die according to claim 9. Further, Lajoie does not specifically disclose the semiconductor die, wherein the at least one of the transistors further comprises a fourth gate insulating layer disposed between the top gate and the second channel layer, and the top gate is spaced apart from the second source electrode and the second drain electrode by the fourth gate insulating layer.
However, Huang discloses the memory device, the transistor further comprises a fourth gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) disposed between the third gate (e.g., the upper gate 110) and the second channel layer, and the third gate is spaced apart from the second source electrode and the second drain electrode (e.g., the upper source/drain regions 106) by the fourth gate insulating layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the semiconductor die of Lajoie/Huang/Ramaswamy/ Park by forming a memory cell as a double -sided memory cell including a stacked transistor structure as taught by Huang to have the semiconductor die, wherein the at least one of the transistors further comprises a fourth gate insulating layer disposed between the top gate and the second channel layer, and the top gate is spaced apart from the second source electrode and the second drain electrode by the fourth gate insulating layer, in order to increase the density of the memory device and to provide improved three-dimensional array of memory cells having vertical stack of memory cells within a footprint of one memory cell (Huang, ¶0026-¶0027).
Regarding claim 16, Lajoie in view of Huang, Ramaswamy, and Park discloses the semiconductor die according to claim 15. Further, Lajoie does not specifically disclose that the first via and second via further penetrates through the second gate insulating layer, the third gate insulating layer, and the fourth gate insulating layer.
Further, Ramaswamy teaches forming the capacitor electrode structure (52) (Ramaswamy, Figs. 1-2, ¶0041-¶0042) of the capacitors (34) having first electrodes (46) electrically connected to the lower first source/drain regions (20) and the upper first source/drain region (20) of the stacked transistor structures, and the sense line (56) (Ramaswamy, Figs. 1-2, ¶0042-¶0043) extend through the stacked memory cells including the second gate insulating layer (28) (Ramaswamy, Figs. 1-2, ¶0038), the third gate insulating layer (28), and the fourth gate insulating layer (28).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the semiconductor die of Lajoie/Huang/Ramaswamy/ Park by forming the plug/via and the second plug/via extending through the transistor stack as the capacitor electrode structure and the sense electrode extending through the stacked memory cells as taught by Ramaswamy to have the semiconductor die, wherein the first via and second via further penetrates through the second gate insulating layer, the third gate insulating layer, and the fourth gate insulating layer, in order to provide improved non-volatile memory with individually addressed memory cells and having lager storage capacity with respect to an area occupied by a capacitor, and with increased levels of integration (Ramaswamy, ¶0001-¶0006, ¶0041-¶0043).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0199624 to Huang in view of Ramaswamy (US 2019/0074277) and Park (US 2011/0014754) as applied to claim 17, and further in view of Beigel et al. (US 2019/0206861, hereinafter Beigel).
Regarding claim 18, Huang in view of Ramaswamy and Park discloses the method according to claim 17. Further, Huang discloses the method, wherein forming a stack of alternating gates and channel layers (110/105), comprises:
forming a first gate (e.g., a lower gate 110) (Huang, Fig. 5A, ¶0053, ¶0037);
forming a first gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) over the first gate (110);
forming a first channel layer (105) (Huang, Fig. 5A, ¶0053-¶0054), the first source electrode (106) and the first drain electrode (106) over the first gate insulating layer;
forming a second gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) over the first channel layer (105), the first source electrode and the first drain electrode;
forming a second gate (e.g., a middle gate 110) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041) over the second gate insulating layer;
forming a third gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) over the second gate (e.g., middle gate 110);
forming a second channel layer (e.g., an upper channel region 105) (Huang, Fig. 5A, ¶0053, ¶0030-¶0032), the second source electrode (106) and the second drain electrode (106) over the third gate insulating layer;
forming a fourth gate insulating layer (e.g., a gate dielectric 217 and dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0053, ¶0034, ¶0041-¶0043) over the second channel layer (e.g., upper channel layer 105), the second source electrode and the second drain electrode; and
forming a third gate (e.g., an upper gate 110) (Huang, Fig. 5A, ¶0053, ¶0037) over the fourth gate insulating layer, and wherein
the first gate (e.g., the lower gate 110) is embedded in a first dielectric layer (e.g., dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0043, ¶0041) covered by the first gate insulating layer (217), the second gate (e.g., the middle gate 110) is embedded in a second dielectric layer (207) covered by the third gate insulating layer (217), and the third gate (e.g., the upper gate 110) is embedded in a third dielectric layer (e.g., dielectric material filled in spaces to isolate adjacent gate electrodes) (Huang, Fig. 5A, ¶0043, ¶0041) covering the fourth gate insulating layer (217)..
Further, Huang does not specifically disclose the method, (1) wherein the top surface of the first source electrode substantially levels with the top surface of the first drain electrode and a top surface of the first channel layer, wherein a top surface of the second source electrode substantially levels with top surfaces of the second drain electrode and the second channel layer; (2) wherein the first gate, the second gate and the third gate are electrically connected to one another through a contact via.
Regarding (1), Park teaches forming the stacked transistors (Park, Figs. 2, 9, ¶0006, ¶0030-¶0049, ¶0057-¶0074) with increased degree of integration, wherein transistors are arranged as thin film transistors (TFT), wherein the stacked TFTs improve driving ability, and the top surface of the first source electrode (9s or 21s) substantially levels with the top surface of the first drain electrode (9d or 21d) and a top surface of the first channel layer, and a top surface of the second source electrode (21s or 33s) substantially levels with top surfaces of the second drain electrode (21d or 33d) and the second channel layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Huang/Ramaswamy/Park by forming the stacked TFT transistors as taught by Park to have the method, wherein the top surface of the first source electrode substantially levels with the top surface of the first drain electrode and a top surface of the first channel layer, and a top surface of the second source electrode substantially levels with top surfaces of the second drain electrode and the second channel layer, in order to provide improved memory device including stacked TFTs to improve driving ability of transistors and to increase degree of integration (Park, ¶0006, ¶0036-¶0037).
Regarding (2), Beigel teaches forming a memory device (Beigel, Figs. 1, 9, ¶0006, ¶0024-¶0025, ¶0031-¶0041, ¶0057, ¶0147-¶0165) with increased level of integration and comprising a stack structure (102) including a plurality of decks (104) (e.g., tiers) each individually having thin film transistors, wherein the plurality of decks (104) (Beigel, Figs. 1, 9, ¶0031-¶0034) includes of more than two decks. The thin film transistors include vertical or planar transistors (Beigel, Figs. 1, 9, ¶0056, ¶0162), and the transistors are arranged as top gate transistors, bottom gate transistors, gate all around transistors (GAA) or double gate transistors. The gate structures of the transistors in different decks (Beigel, Figs. 1, 9, ¶0147-¶0159) are connected through the gate contacts (980 and 978) (e.g., the gate electrode 958 of the transistor 950 in the second deck 902 is connected to the gate electrode 917 of the transistor 911 in the first deck) (Beigel, Fig. 9, ¶0159). The semiconductor structure of Beigel including stacked decks comprises CMOS circuits and an amount of interconnect circuitry (e.g., conductive plugs, conductive lines, etc.) from each deck structure to the base control logic structure is reduced (Beigel, Fig. 1, ¶0206).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Huang by forming a plurality of decks/tiers each individually comprising thin film transistors having gate electrodes electrically connected to each other through the interconnect circuitry including conductive plugs as taught by Beigel to have the method, wherein the first gate, the second gate and the third gate are electrically connected to one another through a contact via, in order to provide improved memory device with increased level of integration and reduced amount of interconnect circuitry; and to obtain a 3D stack of active devices having highly efficient wiring layout and coaxial contacts to provide an area efficient connection between a stack of devices (Beigel, ¶0001, ¶0006, ¶0024-¶0025, ¶0161-¶01615, ¶0206).
Regarding claim 19, Huang in view of Ramaswamy and Park, and Beigel discloses the method according to claim 18. Further, Huang does not specifically disclose that the first via and second via further penetrates through the second gate insulating layer, the third gate insulating layer, and the fourth gate insulating layer.
Further, Ramaswamy teaches forming the capacitor electrode structure (52) (Ramaswamy, Figs. 1-2, ¶0041-¶0042) of the capacitors (34) having first electrodes (46) electrically connected to the lower first source/drain regions (20) and the upper first source/drain region (20) of the stacked transistor structures, and the sense line (56) (Ramaswamy, Figs. 1-2, ¶0042-¶0043) extend through the stacked memory cells including the second gate insulating layer (28) (Ramaswamy, Figs. 1-2, ¶0038), the third gate insulating layer (28), and the fourth gate insulating layer (28).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the method of Huang/Ramaswamy/Park/ Beigel by forming the plug/via and the second plug/via extending through the transistor stack as the capacitor electrode structure and the sense electrode extending through the stacked memory cells as taught by Ramaswamy to have the method, wherein the first via and second via further penetrates through the second gate insulating layer, the third gate insulating layer, and the fourth gate insulating layer, in order to provide improved non-volatile memory with individually addressed memory cells and having lager storage capacity with respect to an area occupied by a capacitor, and with increased levels of integration (Ramaswamy, ¶0001-¶0006, ¶0041-¶0043).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891