DETAILED ACTION
This Office Action is in response to the Amendment filed on April 7, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mahji et al. (WO 2018/236361 A1).
In re claim 1, Mahji et al. discloses (fig. 7) a method for manufacturing a semiconductor structure, comprising: forming a first dielectric layer (750) over a substrate (706); forming a transistor (708) covered by the first dielectric layer and including a source/drain structure (710) and a gate structure (708); forming a gate contact (not labeled, under 734) to electrically connect the gate structure and a source/drain contact (730, 732) to electrically connect the source/drain structure; and forming a first metal line (734) on the gate contact and a second metal line (772) on the source/drain structure; forming a ferroelectric layer (712) (switching layer 712 is a known ferroelectric material; see the translated portion below) on the second metal line; spacer (714) comprising a hole over the ferroelectric layer, and forming a top electrode (726) within the hole; wherein a width of the ferroelectric layer is greater than a width of the top electrode, and a bottom surface of the spacer is in contact with an upper surface of the ferroelectric layer.
In re claim 2, Mahji et al. discloses (fig. 7) wherein the spacer (12) is formed by a single patterning process.
In re claim 3, Mahji et al. discloses (fig. 7) wherein the sidewall of the ferroelectric layer (712) is flush with a sidewall of the second metal line (772).
In re claim 15, Mahji et al. discloses (fig. 7) a method for manufacturing a semiconductor structure, comprising: receiving a substrate (706); forming a source/drain structure (710) of a transistor in the substrate; forming a dielectric layer (750) over the substrate; forming a gate structure (708) of the transistor in the dielectric layer; forming a source/drain contact (730,732) over the source/drain structure; and forming a capacitor (770) electrically connected to the source/drain structure via the source/drain contact, wherein the capacitor includes a ferroelectric layer (switching layer 712 is a known ferroelectric material; see the translated portion below) and a top electrode (726) on the ferroelectric layer, the top electrode having a width less than a width of the ferroelectric layer.
(Translated paragraph)
In an embodiment, for an RRAM bit cell or element, examples of suitable conductive oxides for switching layer 712 include, but are not limited to HfO.sub.x or TaO.sub.x In another embodiment, the conductive oxide layer is composed of a material with two or more metal elements (e.g., as contrasted to common RRAM memories using one metal such as found in binary oxides, such as HfO.sub.x or TaO.sub.x). For example, in an embodiment, the switching layer 712 includes a material such as, but not limited to, ITO (Bi203-.sub.xSn02-.sub.x), In.sub.203-x, sub-stoichiometric yttria doped zirconia (Y203-xZrC>2-x), or Lai-xSr.sub.xGai-.sub.yMg.sub.y03-x-o.5(x+y). In such ternary, quaternary, etc. alloys, the metals used are from adjacent columns of the periodic table. Specific examples of suitable such conductive oxides include, but are not limited to: Y and Zr in Y2O3- .sub.xZr02-.sub.x, In and Sn in In203-.sub.xSn02-.sub.x, or Sr and La in Lai-xSr.sub.xGai-.sub.yMg.sub.y03. Such materials may be viewed as compositions selected to have aliovalent substitution to significantly increase the number of oxygen vacancies.
In re claim 16, Mahji et al. discloses (fig. 7) wherein the forming of the capacitor includes: forming a contact pad (772) over the source/drain contact; forming the ferroelectric layer (712) on the contact pad; and forming the top electrode (726) on the ferroelectric layer.
In re claim 17, Mahji et al. discloses (fig. 7) a sidewall of the ferroelectric layer (712) is aligned with a sidewall of the contact pad (772).
In re claim 18, Mahji et al. discloses (fig. 7) forming a spacer (714) over the ferroelectric layer and surrounding the top electrode.
In re claim 19, Mahji et al. discloses (fig. 7) a sidewall of the spacer (714) is aligned with a sidewall of the ferroelectric layer (712).
In re claim 20, Mahji et al. discloses (fig. 7) inherently, a capacitance of the capacitor is adjusted by a thickness of the spacer, since the structure and materials are the same as the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (WO 2020/129532 A1) in view of Yamazaki (US 6,225,185 B1).
In re claim 1, Kobayashi discloses (Figs. 3A-3D; read translation at section [Method for manufacturing semiconductor memory device]) a method for manufacturing a semiconductor structure, comprising: forming a first dielectric layer (30) over a substrate (10); forming a transistor (TRA) covered by the first dielectric layer and including a source/drain structure (12A2) and a gate structure (21A); forming a gate contact (31A3) to electrically connect the gate structure and a source/drain contact (31A2) to electrically connect the source/drain structure; and forming a first metal line (51A3) on the gate contact and a second metal line (40A) on the source/drain structure; forming a ferroelectric layer (41A) on the second metal line; and forming a top electrode (42A) over the ferroelectric layer. Kobayashi shows all of the elements of the claims except the spacer comprising a hole over the ferroelectric layer, and forming a top electrode within the hole; wherein a width of the ferroelectric layer is greater than a width of the top electrode, and a bottom surface of the spacer is in contact with an upper surface of the ferroelectric layer. Yamazaki discloses (figs. 2A-3C; col. 5, lines 17-25) a method of manufacturing a semiconductor device comprising forming a spacer (12 or 13) comprising a hole (formed in figure 3B) over a ferroelectric layer (10) and forming a top electrode (14) within the hole, wherein a width of the ferroelectric layer is greater than a width of the top electrode (14) (within the hole), and a bottom surface of the spacer (12) is in contact with an upper surface of the ferroelectric layer. With this configuration, prevention of diffusion of oxygen and elements from the ferroelectric capacitor.
In re claim 2, Kobayashi and Yamazaki, when combined, show all of the elements of the claims including wherein the spacer (12) is formed by a single patterning process (Yamazaki, figs. 3A-3B).
In re claim 3, Kobayashi and Yamazaki, when combined, show all of the elements of the claims including wherein the sidewall of the ferroelectric layer (41A) is flush with a sidewall of the second metal line.
In re claim 4, Kobayashi and Yamazaki, when combined, show all of the elements of the claims including wherein the formation of the spacer includes : forming an insulating layer (12; fig. 2C) over the first dielectric layer (6); removing (fig. 3A) a first portion of the insulating layer over the dielectric layer; and removing (fig. 3B) a second portion (contact hole) of the insulating layer over the ferroelectric layer (Yamazaki; figs. 2C-3B).
In re claim 5, Kobayashi and Yamazaki, when combined, show all of the elements of the claims including wherein the removal of the first portion and the removal of the second portion are implemented separately (figs. 3A-3B).
In re claim 6, the references do not specifically disclose the removal of the first portion and the removal of the second portion are implemented simultaneously. However, this limitation is not patentably distinguishable over the cited art since simultaneous removal is the only alternative to separate removal. It would have been obvious to one of ordinary skill in the art at the time the invention was made to perform simultaneous removal instead of separate removal, since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
Claims 7-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Natori et al. (US Pub. 2006/0244022 A1) in view of Kobayashi (WO 2020/129532 A1).
In re claim 7, Natori et al. discloses (figs. 1A-1C; [0021-0034]) a method
for manufacturing a semiconductor structure, comprising: receiving a substrate (S);
forming a transistor (100) on the substrate; forming a first dielectric layer (108) over the transistor forming a source/drain contact (111,115) over a source/drain (107) of the transistor; and forming a plurality of metal lines (117,118,119) over the first dielectric layer; forming a ferroelectric layer (120) over one of the plurality of metal lines which is directly over the source/drain contact; and forming a spacer (125,126,127) and a top electrode (121) laterally surrounded by the spacer on the ferroelectric layer. Natori shows all of the elements of the claims except forming the metal lines spaced apart from each other in a horizontal direction. Kobayashi shows (fig. 1) a plurality of metal lines over a first dielectric layer. The metal lines are spaced apart from each other in a horizontal direction. Then, ferroelectric layer and subsequent components are formed over the metal lines. With this configuration, the semiconductor has proper interconnections and the device is complete. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the semiconductor structure of Natori by forming a plurality of metal lines spaced apart from each other as taught by Kobayashi to complete the device.
In re claim 8, Natori et al. discloses (figs. 1A-1C; [0021-0034]) a sidewall of the ferroelectric layer (120) is flush with a sidewall of the spacer (125,126,127) (since they contact each other).
In re claim 9, Natori and Kobayashi, when combined, disclose all of the elements of the claims. Kobayashi shows (fig. 1) a semiconductor device comprising a plurality of metal lines (40A) and a ferroelectric layer (41A) on the metal lines. The ferroelectric layer is flush with the sidewall of the metal lines.
In re claims 10 and 11, Natori et al. discloses (figs. 1A-1C; [0021-0034]) forming a second dielectric layer (132) over the first dielectric layer (108). The plurality of metal lines (117, 118, 119), the ferroelectric layer (120), and the spacer (125, 126, 127) are embedded in the second dielectric layer (132).
In re claims 12 and 13, Natori and Kobayashi, when combined, disclose all of the elements of the claims, including forming a gate contact (Kobayashi; fig. 1, 31A3) over a gate structure (21A, 321B) of the transistor. The gate contact and the source/drain contact are simultaneously formed (Kobayashi; figs 3A, 3B).
In re claim 14, Natori et al. discloses (figs. 1A-1C; [0021-0034]) the top electrode (121) directly contacts the ferroelectric (121).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815
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