Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 08/01/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US20210135009A1, hereinafter Lin) in view of Mathad et al. (US20020179570A1, hereinafter Mathad).
Regarding claim 1, Lin teaches a method for forming a semiconductor device structure, comprising:
removing a portion of a fin structure to form a first section of an isolation trench in the fin structure (Fig. 2B opening 171 formed by removing portion of filling layer 162 from first and second fin structures 170a/170b);
removing a portion of the surface at a bottom of the first section of the isolation trench using the first etchant (Fig. 2C, par. 68 teaches “a portion of the p-work function layer 158” which lies at a bottom of the first section of opening 171 “is removed by a second etching process 12”);
removing a portion of the substrate to form a second section of the isolation trench by a second etchant (Fig. 2D, par. 70 teaches “a portion of the gate dielectric layer 152 is removed to expose a top surface of the isolation structure 114” at the bottom of openings 171 to form a second section etched away “by a third etching process 13”); and
filling the isolation trench with a dielectric material (Fig. 2E isolation sealing layer 174 filled within the first portion of opening formed by second etching process 12 and the second portion of openings 171 formed by third etching process 13”).
Lin does not appear to teach
passivating exposed surfaces of the first section of the isolation trench to modify an etch selectivity of the exposed surfaces to a first etchant.
Mathad teaches
passivating exposed surfaces of the first section of the isolation trench to modify an etch selectivity of the exposed surfaces to a first etchant (Fig. 2 and par. 7 teaches that “[a] conventional etchant composition for silicon that produces a sidewall passivating deposit includes hydrogen bromide (HBr), oxygen (O2) and a…silicon containing gas, such as silane (SiH4) may be added to increase the silicon content and improve the deposition of the passivating deposit to protect the sidewalls during etching of deep openings.” As the passivation layer is a different composition than substrate 10, the etch selectivity of the exposed surface is modified).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Mathad because the formation of a passivating deposit comprising silicon “protect[s] the sidewalls during etching of deep openings” and so the combination would allow for the formation of a deeper isolation trench through a cyclic etch which results in greater fin isolation (Mathad par. 7)
Regarding claim 2, the combination of Lin and Mathad teaches the method of claim 1,
wherein the etch selectivity of the exposed surfaces is modified by forming a passivation layer on the exposed surfaces of the first section of the isolation trench (As the passivation layer as taught by the above combination of Lin and Mathad is a different composition than substrate 10, the etch selectivity of the exposed surface is modified by the formation of the passivation layer).
Regarding claim 3, the combination of Lin and Mathad teaches the method of claim 2,
wherein the passivation layer is formed by exposing the exposed surfaces of the first section of the isolation trench to a gas mixture comprising a silicon-containing precursor and an oxygen-containing precursor (Mathad par. 7 teaches that “[a] conventional etchant composition for silicon that produces a sidewall passivating deposit includes hydrogen bromide (HBr), oxygen (O2) and a…silicon containing gas, such as silane (SiH4) may be added to increase the silicon content and improve the deposition of the passivating deposit to protect the sidewalls during etching of deep openings” and so the passivation layer is formed by exposure of a gas mixture comprising a silicon precursor, silane, and an oxygen-containing precursor, oxygen).
Regarding claim 4, the combination of Lin and Mathad teaches the method of claim 3,
wherein the gas mixture further comprises a hydrogen halide (Par. 7 teaches that “[a] conventional etchant composition for silicon that produces a sidewall passivating deposit includes hydrogen bromide (HBr)” which is a hydrogen halide).
Regarding claim 5, the combination of Lin and Mathad teaches the method of claim 4,
wherein the passivation layer is a bromine- containing or a hydrogen-containing silicon monoxide (SiO) , SiO2 , or SixNy in amorphous phase (Mathad par. 7 teaches that “[a] conventional etchant composition for silicon that produces a sidewall passivating deposit includes hydrogen bromide (HBr), oxygen (O2) and a…silicon containing gas, such as silane (SiH4) may be added to increase the silicon content and improve the deposition of the passivating deposit to protect the sidewalls during etching of deep openings” and so the passivating deposit 24 as shown in fig. 4 is a bromine containing silicon oxide layer. As Mathad teaches the alternative method of forming the passivating deposit, they also teach the composition of the passivation layer).
Regarding claim 6, the combination of Lin and Mathad teaches the method of claim 1,
wherein the first etchant comprises a bromine- based etch chemistry and an oxygen-based chemistry (Lin par. 69 teaches that “the second etching process 12 is operated by using an etchant, and the etchant includes Cl2, HBr” which includes a bromine-based etch chemistry. Lin additionally teaches in par. 71 that “the third etching process 13 is operated by using an etchant, and the etchant includes…O2.” Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Lin’s second etching process 12 with the inclusion of oxygen because Lin explicitly teaches it as an alternative for the subsequent etching process which occurs in the same trench 171).
Regarding claim 7, the combination of Lin and Mathad teaches the method of claim 6,
wherein the first etchant and the second etchant are substantially the same (Lin pars. 69 and 71 which outline the types of etchant suitable for etching processes 12/13 include several of the same etchants, such as BCl3, and so the combination of Lin and Mathad teaches embodiments in which the etchants used in etching processes 12/13 are substantially the same).
Regarding claim 9, the combination of Lin and Mathad teaches the method of claim 1,
wherein first section of the isolation trench has a first diameter and the second section of the isolation trench has a second diameter that is substantially the same as the first diameter (Lin figs. 2C-D illustrate the first portion of opening formed by second etching process 12 and the second portion of openings 171 formed by third etching process 13 which have substantially the same diameter).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lin (US20210135009A1) and Mathad (US20020179570A1) as applied to claim 1 above, and further in view of Douglas (US4984039A).
Regarding claim 8, the combination of Lin and Mathad teaches the method of claim 1.
The combination of Lin and Mathad does not appear to teach
applying a first bias voltage to a substrate pedestal while removing the portion of the substrate; and
applying a second bias voltage to the substrate pedestal while removing a portion of the passivated surface, wherein the second bias voltage is greater than the first bias voltage.
Douglas teaches that the “[u]se of lower bias voltage [in a trench etch] will reduce sidewall oxide deposition and etch rate, and (if much lower) will begin to lead to isotropic etching characteristics. Use of a higher bias will increase sidewall oxide deposition and etch rate, but will also increase erosion of the oxide mask, which if excessive can lead to loss of linewidth control.
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lin and Mathad with the teachings of Douglas because, as the magnitude of a bias voltage applied during an etch affects the etching characteristics, the voltages applied during the trench etching steps as taught by the above combination of Lin and Mathad are results effective variables that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B)).
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US20210135009A1) in view of Chien et al. (US20220102274A1, hereinafter Chien).
Regarding claim 21, Lin teaches a method for forming a semiconductor device structure, comprising:
forming a sacrificial layer over a substrate (Fig. 1D isolation structure 114 formed over substrate 102);
forming a stack of semiconductor layers over the sacrificial layer, the stack comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked (Lin fig. 1A plurality of first and second alternating layers 104/106 formed into a stack);
forming a fin structure from the stack of semiconductor layers (Fig. 1D first and second fins 110a/110b);
forming an epitaxial source/drain feature adjacent the fin structure (Fig. 1G source/drain structure 138 formed adjacent to first and second fins 110a/110b);
forming an isolation trench extending through the fin structure and into the substrate, wherein the isolation trench is filled with a dielectric material (Fig. 2E isolation sealing layer 174 filled within the first portion of opening formed by second etching process 12 and the second portion of openings 171 formed by third etching process 13”).
Lin does not appear to teach
forming a front side interconnect structure over a front side of the substrate;
removing the substrate from a backside of the substrate until the sacrificial layer is exposed; and
forming a backside via contact from the backside of the substrate, the backside via contact extending towards and in contact with the epitaxial source/drain feature.
Chien teaches a frontside interconnect structure 260 as illustrate in fig. 15C and in par. 15 they additionally teach that “[b]y forming the backside sacrificial contact via, a large contact area may be reserved between an S/D epitaxial feature and backside power rails, effectively reducing contact resistance and improving device performance.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove portions of Lin’s substrate 102 such that a backside via contact is formed from the backside of the substrate and the backside via contact extending towards and in contact with the epitaxial source/drain feature because “a large contact area may be reserved between an S/D epitaxial feature and backside power rails, effectively reducing contact resistance and improving device performance” (Chien par. 15). It would have been further obvious to add a frontside contact structure as taught by Chien to Lin because the combination allows for simultaneous control of the frontside and backside of a semiconductor structure such as the one taught by Lin.
Regarding claim 22, the combination of Lin and Chien teaches the method of claim 21,
wherein the backside via contact and the isolation trench are parallelly arranged and separated from each other by a constant gap along boundaries of the backside via contact and the isolation trench (Chien figs. 14C/26 illustrates isolating ILD 248 being arranged with parallel sidewalls to and separated from backside contact via 282 by a constant gap. Therefore, the combination of Lin and Chien would also teach this configuration).
Regarding claim 23, the combination of Lin and Chien teaches the method of claim 21, further comprising:
performing a planarization process on the backside of the substrate after forming the backside via contact, wherein after the planarization process, a bottom surface of the dielectric material in the isolation trench, a bottom surface of the backside via contact, and a bottom surface of the substrate are substantially co-planar (Chien par. 19 further teaches that “[a] planarization operation, such as a chemical mechanical polishing (CMP) process, may also be performed to remove excessive dielectric material to expose a top surface of the overlaying semiconductor layer 208.” Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lin and Chien with additional teachings from Chien and perform a planarization process on the backside contact structure as taught in above claim 21 because the use of a planarizing process removes residual deposits left from previous steps and reduces defects).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lin (US20210135009A1) and Chien (US20220102274A1) as applied to claim 21 above, and further in view of Mathad (US20020179570A1).
Regarding claim 24, the combination of Lin and Chien teaches the method of claim 21.
The combination of Lin and Chien does not appear to teach wherein forming the isolation trench comprises a cyclic etch process, the cyclic etch process comprising:
etching a portion of the fin structure to form a trench;
forming a passivation layer on sidewalls and a bottom surface of the trench to modify an etch selectivity of the sidewalls;
removing the passivation layer from the bottom surface of the trench; and
etching the substrate to extend the trench.
Mathad teaches wherein forming the isolation trench comprises a cyclic etch process, the cyclic etch process comprising:
etching a portion of the fin structure to form a trench (Fig. 1 opening 14 etched);
forming a passivation layer on sidewalls and a bottom surface of the trench to modify an etch selectivity of the sidewalls (Fig. 2 passivating deposit 24 formed on sidewalls and bottom surface of an isolation trench 14);
removing the passivation layer from the bottom surface of the trench (Fig. 3 passivating deposit 24 removed from bottom of isolation trench 14 and exposing a portion of substrate 10); and
etching the substrate to extend the trench (Fig. 4 trench 14 extended to a further depth).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lin and Chien with the teachings of Mathad because the formation of a passivating deposit comprising silicon “protect[s] the sidewalls during etching of deep openings” and so the combination would allow for the formation of a deeper isolation trench through a cyclic etch which results in greater fin isolation (Mathad par. 7).
Allowable Subject Matter
Claims 10-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10 and its dependent claims. The closest prior art (US20210135009A1, US20020179570A1, US20220102274A1) teaches a method for forming a semiconductor device structure, comprising:
(1) forming a first fin structure and a second fin structure on a first side of a substrate, each first and second fin structure comprising a plurality of a first semiconductor layers and a plurality of a second semiconductor layers alternatingly stacked (Lin figs. 1A-1B illustrate formation of first and second fins 110a/110b comprising a plurality of first and second alternating layers 104/106);
(2) forming a source/drain feature on the first side of the substrate between the first fin structure and the second fin structure (Lin fig. 1G source/drain structures 138 formed on first and second fins 110a/110b);
(3) removing portions of the plurality of the first semiconductor layers and the plurality of the second semiconductor layers from the first fin structure to form an isolation trench having a first depth (Lin fig. 2B opening 171 formed by removing portion of filling layer 162 from first and second fin structures 170a/170b);
(4) forming a passivation layer on sidewalls and a bottom surface of the isolation trench (Mathad fig. 2 passivating deposit 24 formed on sidewalls and bottom surface of an isolation trench 14);
(5) removing the passivation layer from the bottom surface of the isolation trench to expose a portion of the substrate (Mathad fig. 3 passivating deposit 24 removed from bottom of isolation trench 14 and exposing a portion of substrate 10);
(6) removing the passivation layer and the portion of the substrate to extend the isolation trench from the first depth to a second depth (Mathad fig. 4 trench 14 extended to a further depth);
(7) filling the isolation trench with a dielectric material (Lin fig. 2E isolation sealing layer 174 filled within the first portion of opening formed by second etching process 12 and the second portion of openings 171 formed by third etching process 13”);
(8) removing the plurality of the second semiconductor layers from the second fin structure (Lin par. 52 teaches that “[s]ince the first semiconductor layers 104 and the second semiconductor layers 106 are made of different materials, they have different etching selectivity. Therefore, the first semiconductor layers 104 are removed, but the second semiconductor layers 106 are left”);
(9) surrounding each of the first semiconductor layer of the second fin structure with a gate electrode layer (Lin fig. 2G filling layers 162a/162b formed over fins 101a/101b, respectively)
(10) forming an opening from a second side of the substrate to expose the source/drain feature; and
(11) filling the opening with a conductive material to form a backside via contact for the source/drain feature (Chien par. 15 teaches that “[b]y forming the backside sacrificial contact via, a large contact area may be reserved between an S/D epitaxial feature and backside power rails, effectively reducing contact resistance and improving device performance” and so a person of ordinary skill would be motivated to create a backside contact and add it to the combination of Lin and Mathad because “a large contact area may be reserved between an S/D epitaxial feature and backside power rails, effectively reducing contact resistance and improving device performance”).
However, the closest prior art does not teach in combination with the other claimed elements
wherein the isolation trench and the backside via contact are parallelly arranged and separated from each other by a constant gap along the boundaries of the isolation trench and the backside via contact.
Examiner notes that while there are embodiments within the prior art, see above combination of Lin, Mathad, and Chien, that teach the formation of an isolation structure through the use of a cyclic etch within a FinFET having a backside contact, such a combination with an extended isolation trench etch as taught by Mathad would not necessarily result in a parallel and constant offset configuration with the backside trench as taught by Chien. Therefore, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that the isolation trench and the backside via contact are parallelly arranged and separated from each other by a constant gap along the boundaries of the isolation trench and the backside via contact in addition with the other limitations of the independent claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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