DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group II, Species 4 (claims 16-35) in the reply filed on July 2, 2026 is acknowledged.
Information Disclosure Statement
The references cited within the IDS document (dated June 9, 2025) have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2022/0216128 A1, hereinafter referred to as ‘Zhang’).
As to claim 16, Zhang teaches a method (see figures 1-3D) for forming a chip package structure, comprising:
forming a chip structure (102) to have a device layer arranged along a front surface (102a) of a substrate, the device layer having a hot spot region;
etching a back surface of the substrate (see figure 3B) to form a recess over the hot spot region;
bonding the front surface of the chip structure to a carrier substrate (104); and
bonding a heat dissipation lid to the back surface of the substrate, wherein the heat dissipation lid has a plate portion (flat upper part 210) and a protruding portion (204) under the plate portion, the plate portion is over the back surface of the substrate, and the protruding portion is in the recess of the back surface of the substrate.
As to claim 21, Zhang teaches a method (see figures 1-3D) for forming a chip package structure, comprising:
forming a chip structure (102) to have a device layer arranged along a front surface (102a) of a substrate, wherein the substrate has a recessed surface (shown in figure 3B) that is coupled to a back surface of the substrate by interior sidewalls of the substrate, the back surface wrapping around the recessed surface in a top-view;
bonding the chip structure to a carrier substrate (104), wherein the front surface of the substrate faces the carrier substrate after bonding; and
attaching a heat dissipation lid (210/204) to the back surface of the substrate, wherein the heat dissipation lid continuously extends from over the back surface of the substrate to along the interior sidewalls of the substrate.
Allowable Subject Matter
Claims 17, 20, 22, 27, and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not teach or suggest the disclosed invention regarding:
As to claim 17, the method further comprising: forming a first heat conductive layer in the recess of the back surface of the substrate before the heat dissipation lid is bonded to the back surface of the substrate, wherein the protruding portion of the heat dissipation lid is over the first heat conductive layer.
As to claim 20, the method further comprising: a heat conductive plug penetrating into a portion of the substrate under the recess, wherein the heat conductive plug is electrically insulated from the device layer.
As to claim 22, the method further comprising: forming a first thermal insulating material on the back surface of the substrate prior to attaching the heat dissipation lid to the back surface of the substrate.
As to claim 27, the method further comprising: wherein the recessed surface has an elongated rectangular shape in the top-view.
As to claim 28, the method further comprising: forming a ring structure onto the carrier substrate; and attaching the heat dissipation lid to the ring structure by way of an adhesive layer.
Claims 18, 19, and 23-26 are also objected to as being further dependent upon the above-identified objected claims.
Claims 29-35 are allowable.
The following is an examiner’s statement of reasons for allowability.
The prior art of record does not teach or suggest the disclosed invention regarding a method for forming a chip package structure, particularly characterized by comprising:
wherein the integrated chip structure has a recessed region along a backside of the integrated chip structure opposing the frontside;
forming a first thermal insulating material on the backside of the integrated chip structure;
forming a second thermal insulating material within the recessed region of the integrated chip structure; and
attaching a heat dissipation lid to the first thermal insulating material and the second thermal insulating material, wherein the heat dissipation lid comprises a lower surface and sidewalls that extend outward from the lower surface to within the recessed region, as recited within claim 29. Claims 30-25 depend from claim 29.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000.
/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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