DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 102 3
A. Claims 1, 2, 4, 5, 15, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0278806 (“Kuo”). 3
B. Claims 8, 9, 14-16, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2016/0111325 (“JangJian”). 6
III. Claim Rejections - 35 USC § 103 8
A. Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo. 9
B. Claims 1, 2, 4, 5, 7, 15, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of US (“Sekar”). 10
C. Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over JangJian. 12
IV. Allowable Subject Matter 13
V. Pertinent Prior Art 14
Conclusion 15
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1, 2, 4, 5, 15, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0278806 (“Kuo”).
With regard to claim 1, Kuo discloses, generally in Fig. 4,
1. An interconnect structure, comprising:
[1] a first dielectric layer [e.g. “metal layer 104b” (¶ 31); see discussion below] disposed over one or more devices 128 [¶ 25];
[2] a first conductive feature 146a [¶ 32] disposed in the first dielectric layer 104b;
[3] a second dielectric layer [“via layer 106c” (¶ 31); see discussion below] disposed over the first dielectric layer 104b and the first conductive feature 146a;
[4a] a second conductive feature Via2 [¶ 32] disposed in the second dielectric layer 106c,
[4b] wherein the second conductive feature Via2 is electrically connected to the first conductive feature 146a [as shown in Fig. 4]; and
[5a] a heat dissipation layer 122(120) [¶ 31] disposed between the first 104b and second 106c dielectric layers,
[5b] wherein the heat dissipation layer 122(120) partially surrounds the second conductive feature Via2 and is electrically isolated from the first 146a and second Via2 conductive features [¶ 31].
With regard to features [1] and [3] of claim 1, while Kuo does not state from what material the portion of each of the “via layer[s]” 106a-106d and each of the “metal layer[s]” 104a-104d (e.g. ¶ 25), other than the portions that are the metal vias 140b, Via1, Via2, Via3 (¶ 26) and the metal lines 146a-146d (¶ 32), themselves, are made, it is necessarily inherently electrically insulating; otherwise, the “conductive metal material 122” of the “continuous ground shielding layer 120” and the metal vias 140b, Via1, Via2, Via3 (¶ 26) and metal lines 146a-146d (¶ 32) would electrically short with each other, rendering the device useless. As such, the burden of proof is shifted to Applicant to prove the contrary, i.e. that the portion of each of the “via layer[s]” 106a-106d and each of the “metal layer[s]” 104a-104d (e.g. ¶ 25), other than the portions that are the metal vias 140b, Via1, Via2, Via3 (¶ 26) and the metal lines 146a-146d (¶ 32), is somehow not a dielectric material. (See MPEP 2112(I)-(V).)
With regard to feature [5a] of claim 1, because the “ground shielding layer 120” is made of “conductive metal material 122”, while the surrounding material of the “via layers 106a-106d” and “metal layers 104a-104d” is necessarily electrically insulating, it is held, absent evidence to the contrary that the “conductive metal material 122” is capable of functioning as the claimed “heat dissipation layer”. Evidence is the metals are known to be electrically and thermally conducting while dielectrics typically used in making interconnect layers and redistribution layers are thermally insulating, as evidenced in the Instant Application (Instant Specification: ¶¶ 24, 30; Fig. 2). As such, the burden of proof is shifted to Applicant to prove the contrary, i.e. that the “conductive metal material 122” is somehow not capable of functioning a heat dissipation layer. (See MPEP 2112(I)-(V).)
This is all of the limitations of claim 1.
With regard to claim 2, 4, and 5, Kuo further discloses,
2. The interconnect structure of claim 1, wherein the second conductive feature Via2 is a conductive via having a first height, and the heat dissipation layer 122 has a second height substantially less than the first height [as shown in Fig. 4].
4. The interconnect structure of claim 2, wherein the second conductive feature Via2 is partially disposed in an opening [shown but not labeled in Fig. 4] in the heat dissipation layer 122(120).
5. The interconnect structure of claim 4, wherein the second conductive feature Via2 has a first width, and the opening has a second width substantially greater than the first width [as shown in Fig. 4].
With regard to claims 15 and 19, Kuo discloses, generally in Fig. 4,
15. An interconnect structure, comprising:
[1] a first dielectric layer [e.g. “metal layer 104b”] disposed over a substrate 130 [¶ 25];
[2] a first conductive feature 146a disposed in the first dielectric layer 104b;
[3] a second dielectric layer [e.g. via layer 106c”] disposed over the first dielectric layer 104b and the first conductive feature 146a;
[4a] a second conductive feature M2 disposed in the second dielectric layer 106c/104c,
[4b] wherein the second conductive feature M2 comprises a conductive line 146c disposed over a conductive via Via2 [¶¶ 31-32]; and
[5a] a heat dissipation layer 122(120) disposed between the first conductive feature 146a and the conductive line 146c [as shown in Fig. 4],
[5b] wherein the heat dissipation layer 122(120) partially surrounds the conductive via Via2 and is electrically isolated from the first 146a and second 146c conductive features [as shown in Fig. 4; ¶ 31].
19. The interconnect structure of claim 15, wherein the conductive via Via2 has a first height, and the heat dissipation layer 122(120) has a second height substantially less than the first height [as shown in Fig. 4].
B. Claims 8, 9, 14-16, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2016/0111325 (“JangJian”).
With regard to claim 8, JangJian discloses, generally in Fig. 12,
8. An interconnect structure, comprising:
[1] a first dielectric layer 30 disposed over one or more devices 22 [¶ 15];
[2] a first conductive feature 36 [¶ 20] disposed in the first dielectric layer 30;
[3] a first etch stop layer 40a [¶¶ 23-24] disposed on the first conductive feature 36 and the first dielectric layer 30;
[4] a heat dissipation layer 40b [¶¶ 25-27] disposed on the first etch stop layer 40a;
[5] a second etch stop layer 40c [¶¶ 28-30] disposed on the heat dissipation layer 40b;
[5] a second dielectric layer 42 [¶ 34] disposed on the second etch stop layer 40c; and
[6] a second conductive feature 48/50 [¶ 39] disposed in the second dielectric layer 42,
wherein
[7] the second conductive feature 48/50 is electrically connected to the first conductive feature 36, and
[8] the heat dissipation layer 40b is electrically isolated from the first 36 and second 48/50 conductive features [because 40b is made of a dielectric material, e.g. aluminum nitride].
With regard to feature [4] of claim 8, it is held, absent evidence to the contrary that the aluminum nitride layer 40b of 5 Å to 70 Å thick (i.e. 0.5 nm to 7 nm) is capable of functioning as a heat dissipation layer as evidenced by the Instant Application, which discloses that the heat dissipation layer can be aluminum nitride (Instant Specification: ¶ 29) and can be from 3 nm to 8 nm thick (instant claim 12, infra). As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
This is all of the limitations of claim 8.
With regard to claims 9 and 14, JangJian further discloses,
9. The interconnect structure of claim 8, wherein the first and second conductive features each comprises Cu, and the heat dissipation layer comprises Ru, W, Al, or Ag [AlN comprises Al].
14. The interconnect structure of claim 8, wherein the one or more devices 22 comprises one or more transistors [¶ 15: “Complementary Metal-Oxide Semiconductor (CMOS) transistors …”].
With regard to claims 15, 16, 19, and 20, JangJian discloses, generally in Fig. 12,
15. An interconnect structure, comprising:
[1] a first dielectric layer 30 disposed over a substrate 20 [¶¶ 15, 18] ;
[2] a first conductive feature 36 disposed in the first dielectric layer 30;
[3] a second dielectric layer 42 disposed over the first dielectric layer 30 and the first conductive feature 36;
[4a] a second conductive feature 48/50 disposed in the second dielectric layer 30,
[4b] wherein the second conductive feature 48/50 comprises a conductive line 50 disposed over a conductive via 48 [¶ 39]; and
[5a] a heat dissipation layer 40b disposed between the first conductive feature 36 and the conductive line 50,
[5b] wherein the heat dissipation layer 40 partially surrounds the conductive via 48 and is electrically isolated from the first 46 and second 48/50 conductive features [because 40b is made of a dielectric material, e.g. aluminum nitride].
16. The interconnect structure of claim 15, further comprising a first etch stop layer 40a in contact with the first conductive feature 36 and the heat dissipation layer 40b.
19. The interconnect structure of claim 15, wherein the conductive via 48 has a first height, and the heat dissipation layer 40b has a second height substantially less than the first height [as shown in Fig. 12].
20. The interconnect structure of claim 19, wherein the first and second conductive features each comprises Cu, and the heat dissipation layer comprises Ru, W, Al, or Ag [AlN comprises Al].
III. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo.
Claim 3 reads,
3. The interconnect structure of claim 2, wherein the second height is about 20 percent to about 50 percent of the first height.
The prior art of Kuo, as explained above, discloses each of the features of claims 1 and 2.
Because the “conductive metal material 122” layers of the “continuous ground shielding layer 120” are formed directly adjacent to the via Via2 and between metal lines, 146a and 146c, and is shown to be and must necessarily be thinner than the via in order to prevent physically contacting the metal lines, 146a and 146c, the height of the via Via2 is necessarily between 0 and 100 percent of the height of the via. As such, the claimed “second height” range falls within the range disclosed in the prior art.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
Claim 6 reads,
6. The interconnect structure of claim 5, wherein the second width is about 50 percent to about 500 percent greater than the first width.
Kuo does not give an amount by which the width of the opening, i.e. the “second width” in which both the Via2 and insulating material 104c/106c that space the heat dissipating layer 122(120) from Via2, i.e. the claimed “second conductive feature”.
The claimed range is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. See In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art).
B. Claims 1, 2, 4, 5, 7, 15, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of US 2012/0306082 (“Sekar”).
With regard to claims 1 and 15, while Examiner maintains that metal layer 122 of Kuo inherently are capable of functioning as a heat dissipation layer for the reasons explained in the rejection under 35 USC 102(a) over Kuo, to the extent that Applicant may provide proof that they are not, then this would be a difference between Kuo and each of claims 1 and 15.
Sekar teaches a semiconductor device including a wafer 3310 having transistors (“for example, MOSFETS, FinFets, FD-RCATs, BJTs, HEMTs, and/or HBTs” as well as “fully functional circuitry including metal layers (including aluminum or copper metal interconnect layers that may connect acceptor wafer 3310 transistors)” (¶ 127; Figs. 33A-33B). Like Kuo, Fig. 33A of Sekar shows a “shield/heat sink layer 3388” made from “Aluminum, Tungsten, Copper, silicon or cobalt based silicides” (id.; emphasis added) and around the metallization structures including “metal interconnect 3381” and “metal connect pads or strips 3380” (id.) and “shield path via 3383”.
Thus, to the extent that Applicant may provide proof that the metal layer 122 of Kuo does not somehow provide heat dissipation, then it would have been at least obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the metal layer 122 of Kuo from a metal capable of dissipating heat, such as “Aluminum, Tungsten, Copper, silicon or cobalt based silicides” (id.), thereby enabling the ground shielding structure 120 of Kuo to function as a heat sink, as taught by Sekar.
This is all of the limitations of claims 1 and 15.
Explanations form claims 2, 4, 5, 15, and 19remain the same as explained under the rejection over Kuo, alone.
Claims 7 and 20 read,
7. The interconnect structure of claim 1, wherein the first and second conductive features each comprises Cu, and the heat dissipation layer comprises Ru, W, Al, or Ag.
20. The interconnect structure of claim 19, wherein the first and second conductive features each comprises Cu, and the heat dissipation layer comprises Ru, W, Al, or Ag.
Kuo does not give the identity of any of the metals for the vias 140a, 140b, Via1, Via2, Via3, or metal lines 146a-146d or the metal layer 122 making the ground shielding layer 120.
As explained above, Sekar teaches that the metal interconnect of the device can be made from, e.g. copper, and the shield/heat sink layer 3388 can be made from at least aluminum and tungsten.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the vias 140a, 140b, Via1, Via2, Via3 and metal lines 146a-146d of Kuo from Cu and the metal layers 122 of the ground shielding structure 120 of Kuo from Al or W because Sekar explains that these are suitable metals for the same purpose of forming a shield layer but also explains that Al and W also provide the benefit of performing as a heat sink. As such, the metal selection amounts to obvious material choice, based on the evidence of record. (See MPEP 2144.07.)
This is all of the limitations of claims 7 and 20.
C. Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over JangJian.
Claim 12 reads,
12. The interconnect structure of claim 8, wherein the heat dissipation layer has a thickness ranging from about 3 nm to about 8 nm.
JangJian discloses that the thickness T4 (Fig. 6) of the heat dissipating layer 40b can be in the range of 0.5 nm to 7 nm for the heat dissipation layer 40b (¶ 27, supra) overlaps the claimed range.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
Claim 13 reads,
13. The interconnect structure of claim 12, wherein the first and second etch stop layer each has a thickness ranging from about 3 nm to about 10 nm.
JangJian further discloses that the thickness T1 (Fig. 4: ¶ 24) of the first etch stop layer 40a and the thickness T3 (Fig. 6: ¶ 29) of the second etch stop layer 40c are both in the range of 5 Å to 20 Å, i.e. 0.5 nm to 2.0 nm.
Inasmuch as (1) each of the layers 40a and 40c function as etch stop layers, and (2) that there is no evidence that making the claimed first and second etch stop layers form 3 nm to 10 nm provides unexpected results relative to the prior art range, these claimed ranges are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. See In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art).
IV. Allowable Subject Matter
Claims 10, 11, 17, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 10, 11, and 17 read,
10. The interconnect structure of claim 9, wherein the first etch stop layer and the second etch stop layer each comprises an aluminum nitride and aluminum oxide bilayer structure.
11. The interconnect structure of claim 9, wherein the first etch stop layer comprises SiCN and the second etch stop layer comprises an aluminum nitride and aluminum oxide bilayer structure.
17. The interconnect structure of claim 16, further comprising a second etch stop layer in contact with the heat dissipation layer, the first etch stop layer, and the conductive via.
The prior art does not reasonably teach or suggest—in the context of each of claims 10, 11, and 17—the limitations recited therein.
Claim 18 would be allowable for including the same limitations by depending from claim 17.
V. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2020/0106008 (“Peng”) is cited for disclosing at least all of the limitations of each of independent claims 1, 8, and 15. See Fig. 18, particularly the etch stop layer 16(=16A/16B/16C) and the associated text.
US 9,659,811 (“Peng”) is cited for disclosing at least all of the limitations of each of independent claims 1, 8, and 15. See Figs. 1A-1C and 19, especially Fig. 1C teaching a triple layer etch stop 80/70/170, and the associated text.
US 2021/0005548 (“Lee”) is cited for disclosing at least all of the limitations of each of independent claims 1, 8, and 15. See Fig. 6 and the associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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