DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Objections 3
III. Claim Rejections - 35 USC § 103 3
A. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0278806 (“Kuo”) in view of US 2020/0006370 (“Huo”). 3
B. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of Huo and US 2012/0306082 (“Sekar”). 9
IV. Allowable Subject Matter 10
V. Response to Arguments 11
Conclusion 11
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Objections
In claim 18, line 1, replace “claim 17” with “claim 15” because the limitations of claim 17 were incorporated into claim 15.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0278806 (“Kuo”) in view of US 2020/0006370 (“Huo”).
Claim 1 reads,
1. (Currently Amended) An interconnect structure, comprising:
[1] a first dielectric layer disposed over one or more devices;
[2] a first conductive feature disposed in the first dielectric layer;
[3] a second dielectric layer disposed over the first dielectric layer and the first conductive feature;
[4a] a second conductive feature disposed in the second dielectric layer,
[4b] wherein the second conductive feature is electrically connected to the first conductive feature; and
[5a] a heat dissipation layer disposed between the first and second dielectric layers, wherein
[5b] the heat dissipation layer partially surrounds the second conductive feature and is electrically isolated from the first and second conductive features, and
[5c] the heat dissipation layer is a metal layer having a thickness ranging from about 3 nm to about 8 nm.
With regard to claim 1, Kuo discloses, generally in Fig. 4,
1. An interconnect structure, comprising:
[1] a first dielectric layer [e.g. “metal layer 104b” (¶ 31); see discussion below] disposed over one or more devices 128 [¶ 25];
[2] a first conductive feature 146a [¶ 32] disposed in the first dielectric layer 104b;
[3] a second dielectric layer [“via layer 106c” (¶ 31); see discussion below] disposed over the first dielectric layer 104b and the first conductive feature 146a;
[4a] a second conductive feature Via2 [¶ 32] disposed in the second dielectric layer 106c,
[4b] wherein the second conductive feature Via2 is electrically connected to the first conductive feature 146a [as shown in Fig. 4]; and
[5a] a heat dissipation layer 122(120) [¶ 31] disposed between the first 104b and second 106c dielectric layers,
[5b] wherein the heat dissipation layer 122(120) partially surrounds the second conductive feature Via2 and is electrically isolated from the first 146a and second Via2 conductive features [¶ 31], and
[5c] … [not taught] … .
With regard to features [1] and [3] of claim 1, while Kuo does not state from what material the portion of each of the “via layer[s]” 106a-106d and each of the “metal layer[s]” 104a-104d (e.g. ¶ 25), other than the portions that are the metal vias 140b, Via1, Via2, Via3 (¶ 26) and the metal lines 146a-146d (¶ 32), themselves, are made, it is necessarily inherently electrically insulating; otherwise, the “conductive metal material 122” of the “continuous ground shielding layer 120” and the metal vias 140b, Via1, Via2, Via3 (¶ 26) and metal lines 146a-146d (¶ 32) would electrically short with each other, rendering the device useless. As such, the burden of proof is shifted to Applicant to prove the contrary, i.e. that the portion of each of the “via layer[s]” 106a-106d and each of the “metal layer[s]” 104a-104d (e.g. ¶ 25), other than the portions that are the metal vias 140b, Via1, Via2, Via3 (¶ 26) and the metal lines 146a-146d (¶ 32), is somehow not a dielectric material. (See MPEP 2112(I)-(V).)
With regard to feature [5a] of claim 1, because the “ground shielding layer 120” is made of “conductive metal material 122”, while the surrounding material of the “via layers 106a-106d” and “metal layers 104a-104d” is necessarily electrically insulating, it is held, absent evidence to the contrary that the “conductive metal material 122” is capable of functioning as the claimed “heat dissipation layer”. Evidence is the metals are known to be electrically and thermally conducting while dielectrics typically used in making interconnect layers and redistribution layers are thermally insulating, as evidenced in the Instant Application (Instant Specification: ¶¶ 24, 30; Fig. 2). As such, the burden of proof is shifted to Applicant to prove the contrary, i.e. that the “conductive metal material 122” is somehow not capable of functioning a heat dissipation layer. (See MPEP 2112(I)-(V).)
With regard to feature [5c] of claim 1,
[5c] the heat dissipation layer is a metal layer having a thickness ranging from about 3 nm to about 8 nm.
Kuo does not provide a thickness for the “ground shielding layer 120” made of “conductive metal material 122”.
Huo, like Kuo, teaches a semiconductor device 100 having an interconnect structure 110, 134 with a “shielding layer 102” made of “conductive regions 148” that may be metal (Huo: ¶ 47) surrounding the metal vias 152 and between metal interconnect layers 112, 142 (Huo: Fig. 1A, ¶¶ 35, 44, 47). Also like Kuo, the shielding layer 102 may be grounded 154 (Huo: ¶ 53). Huo further discloses that the thickness of the shielding layer 102 made of metal regions 148 may have a thickness of 1 nm to 1 μm, “e.g., 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, …” (Huo: ¶ 48).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the shielding layer in Kuo to be e.g. 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, because Huo teaches that this is a suitable thickness for a shielding layer built into the interconnect, as in Kuo.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
This is all of the limitations of claim 1.
With regard to claim 2, 4, and 5, Kuo further discloses,
2. (Original) The interconnect structure of claim 1, wherein the second conductive feature Via2 is a conductive via having a first height, and the heat dissipation layer 122 has a second height substantially less than the first height [as shown in Fig. 4].
4. (Original) The interconnect structure of claim 2, wherein the second conductive feature Via2 is partially disposed in an opening [shown but not labeled in Fig. 4] in the heat dissipation layer 122(120).
5. (Original) The interconnect structure of claim 4, wherein the second conductive feature Via2 has a first width, and the opening has a second width substantially greater than the first width [as shown in Fig. 4].
Claim 3 reads,
3. The interconnect structure of claim 2, wherein the second height is about 20 percent to about 50 percent of the first height.
The prior art of Kuo, as explained above, discloses each of the features of claims 1 and 2.
Because the “conductive metal material 122” layers of the “continuous ground shielding layer 120” are formed directly adjacent to the via Via2 and between metal lines, 146a and 146c, and is shown to be and must necessarily be thinner than the via in order to prevent physically contacting the metal lines, 146a and 146c, the height of the via Via2 is necessarily between 0 and 100 percent of the height of the via. As such, the claimed “second height” range falls within the range disclosed in the prior art.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
Claim 6 reads,
6. The interconnect structure of claim 5, wherein the second width is about 50 percent to about 500 percent greater than the first width.
Kuo does not give an amount by which the width of the opening, i.e. the “second width” in which both the Via2 and insulating material 104c/106c that space the heat dissipating layer 122(120) from Via2, i.e. the claimed “second conductive feature”.
The claimed range is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. See In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art).
Claim 7 reads,
7. (Original) The interconnect structure of claim 1, wherein
[1] the first and second conductive features each comprises Cu, and
[2] the heat dissipation layer comprises Ru, W, Al, or Ag.
Kuo does not give the identity of any of the metals for the vias 140a, 140b, Via1, Via2, Via3, or metal lines 146a-146d or the metal layer 122 making the ground shielding layer 120.
Huo further discloses that the conductive regions 148 of the shielding layer 102 can be made from any of Ru, W, Al, and Ag, inter alia (Huo: ¶ 47) and that the metal lines 112 and metal vias 114 can be made from copper (Cu), inter alia (Huo: ¶ 36).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the metal layer 122 forming the shielding layer 120 from any of Ru, W, Al, and Ag and the metals for the vias 140a, 140b, Via1, Via2, Via3, and metal lines 146a-146d from Cu because Huo teaches that these metals are suitable for the same elements used for the same purpose. As such, the selection of the specific metals amounts to obvious material choice. (See MPEP 2144.07.)
B. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of Huo and US 2012/0306082 (“Sekar”).
With regard to claims 1 and 7, while Examiner maintains that metal layer 122 of Kuo (or the metal regions 148 of Huo) are inherently capable of functioning as a heat dissipation layer for the reasons explained in the rejection under 35 USC 103 over Kuo in view of Huo, to the extent that Applicant may provide proof that they are not, then this would be a difference between Kuo and each of claim 1.
Sekar teaches a semiconductor device including a wafer 3310 having transistors (“for example, MOSFETS, FinFets, FD-RCATs, BJTs, HEMTs, and/or HBTs” as well as “fully functional circuitry including metal layers (including aluminum or copper metal interconnect layers that may connect acceptor wafer 3310 transistors)” (¶ 127; Figs. 33A-33B). Like Kuo, Fig. 33A of Sekar shows a “shield/heat sink layer 3388” made from “Aluminum, Tungsten, Copper, silicon or cobalt based silicides” (id.; emphasis added) and around the metallization structures including “metal interconnect 3381” and “metal connect pads or strips 3380” (id.) and “shield path via 3383”. The metals in Sekar for the shielding layer are consistent with the metals used in Huo, at least Al, W, and Cu (Huo: ¶ 47).
Thus, to the extent that Applicant may provide proof that the metal layer 122 of Kuo does not somehow provide heat dissipation, then it would have been at least obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the metal layer 122 of Kuo from a metal capable of dissipating heat, such as “Aluminum, Tungsten, Copper, silicon or cobalt based silicides” (id.), thereby enabling the ground shielding structure 120 of Kuo to function as a heat sink, as taught by Sekar.
This is all of the limitations of claim 1.
The limitations of claims 2-7 are the same as explained above.
IV. Allowable Subject Matter
Claims 8-15, 18-21, and 22, pending overcoming the objection to claim 18, are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
(1) With regard to claim 15, Applicant incorporated the limitations from dependent claim 17 along with intervening claim 16 into claim 15, the features of claim 17 having been previously indicated to include allowable subject matter (Non-Final Rejection at pp. 13-14).
Claims 18-20 and 22 are allowable for including the same allowable limitations by depending from claim 15 either directly or indirectly.
(2) With regard to claim 8, Applicant incorporated a portion of the limitations from dependent claim 11 into claim 8, the limitation, i.e. “the second etch stop layer comprises an aluminum nitride and aluminum oxide bilayer structure” was not indicated, in isolation from the other limitations of claim 11 to include allowable subject matter (Non-Final Rejection at pp. 13-14). Nonetheless further search and consideration shows that the prior art does not reasonably teach or suggest—in the context of claim 8—the “the second etch stop layer comprises an aluminum nitride and aluminum oxide bilayer structure”.
Claims 9-14 and 21 are allowed at least for including the same allowable limitations by depending from claim 8 either directly or indirectly.
V. Response to Arguments
Applicant’s arguments filed 08/20/2026 with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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