Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant' s amendment and response filed 8/9/2026 has been entered and made record. This application contains 6 pending claims.
Claims 1-5, and 8 have been amended.
Claims 6 and 7 have been cancelled.
Response to Arguments
Applicant’s arguments filed 8/19/2026 regarding claims rejections under 35 U.S.C. 101 in claim 1-8 have been fully considered but they are not persuasive.
The applicant argues on pages 5-6 of the remark filed on 8/19/2026 that “… Applicant submits that at least the above features of amended claim 1 are not directed to a judicial exception. … These limitations recite activities which are not mental process, because they are not performed in a human mind, they are not observations, evaluations, judgments or opinions. Therefore, Applicant respectfully submits that claim 1 does not constitute an abstract idea.”
The Examiner respectfully disagrees applicant’s argument. The steps of “classify the wafer circuit patterns to be measured into a first type of wafer circuit patterns and a second type of wafer circuit patterns, wherein the first type of wafer circuit patterns”; “aligning the user designed circuit patterns manually with the second type of wafer circuit patterns, then performing measurement twice on the second type of wafer circuit patterns by the electron beam linewidth defect scanning machine to obtain two groups of measurement results”; and “reviewing the two groups of measurement results for the second type of wafer circuit patterns to determine if there is a measurement error” are a mental process, therefore, they are considered to be an abstract idea. A human mind can observe and evaluate of collected information of the classified the wafer circuit patterns that are measured, and a result of comparison between two groups of measurement results for the second type of wafer circuit patterns, and make determination, judgment and have opinion about whether there is a measurement error exist based on the evaluation. Thus, the claim is directed to an abstract idea.
The applicant argues on page 6 of the remark filed that “… Under Step 2A, Prong Two, elements recited in claim 1, non-abstract as shown above, are additionally part of the step 1 to step 5 measurement process, thus they are sufficiently integrated into a practical application. … .”
The Examiner respectfully disagrees applicant’s argument. Practical application can be demonstrated by additional elements that are sufficient to integrate the judicial exception into a practical application. The additional element “for the first type of wafer circuit patterns, performing automatic measurement by the electron beam linewidth defect scanning machine” is considered necessary data gathering and thus, not sufficient to integrate the abstract idea into a practical application. As recited in MPEP section 2106.05(g), necessary data gathering (i.e., obtaining measurement data) is considered extra solution activity in light of Mayo, 566 U.S. at 79, 101 USPQ2d at 1968; OIP Techs., Inc. v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1092-93 (Fed. Cir. 2015).
The additional elements “providing wafer circuit patterns to be measured by an electron beam linewidth defect scanning machine, wherein the wafer circuit patterns are transferred from user designed circuit patterns onto a wafer by a semiconductor process, wherein the user designed circuit patterns may comprise line-end corners, and wherein the electron beam linewidth defect scanning machine has an electron beam scanning range which is a square area, wherein the square area has a side length”; “three scenarios: in a first scenario, a number of the line-end corners is more than 0 in the square area; in a second scenario, the number of the line-end corners in the square area is 0 and a linewidth standard deviation StdWidth equals to 0; in a third scenario, the number of the line-end corners in the square area is 0 and the linewidth standard deviation StdWidth is equal to or greater than 0.006, wherein the first type of wafer circuit patterns is measurable automatically by the electron beam linewidth defect scanning machine, and wherein the second type of wafer circuit patterns has zero line-end corners in the square area and the linewidth standard deviation StdWidth is between 0 and 0.006, and wherein the second type of wafer circuit patterns is not measurable automatically by the electron beam linewidth defect scanning machine”; and “if there is a measurement error, repeat step 3 on the second type of wafer circuit patterns with the measurement error; if there is no measurement error; and analyzing the measurement results” are not sufficient to integrate the abstract idea into a practical application. Therefore, the current claim does not recite additional elements that are indicative of integration of an abstract idea into a practical application.
Dependent claims 2-8 provide additional features/steps which are considered part of an expanded abstract idea of the independent claims, and do not integrate the abstract ideas into a practical application. Therefore, claims 2-8 are also patent ineligible.
Hence, the Examiner submits that the rejections of Claims 1-8 are proper.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-5, and 8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
As to claim 1, the claim recites “A method for reducing measurement errors of critical pattern dimensions of polycrystal layers, at least comprising:
step 1: providing wafer circuit patterns to be measured by an electron beam linewidth defect scanning machine, wherein the wafer circuit patterns are transferred from user designed circuit patterns onto a wafer by a semiconductor process, wherein the user designed circuit patterns may comprise line-end corners, and wherein the electron beam linewidth defect scanning machine has an electron beam scanning range which is a square area, wherein the square area has a side length;
step 2: defining rules to classify the wafer circuit patterns to be measured into a first type of wafer circuit patterns and a second type of wafer circuit patterns, wherein the first type of wafer circuit patterns comprises three scenarios: in a first scenario, a number of the line-end corners is more than 0 in the square area; in a second scenario, the number of the line-end corners in the square area is 0 and a linewidth standard deviation StdWidth equals to 0; in a third scenario, the number of the line-end corners in the square area is 0 and the linewidth standard deviation StdWidth is equal to or greater than 0.006, wherein the first type of wafer circuit patterns is measurable automatically by the electron beam linewidth defect scanning machine, and wherein the second type of wafer circuit patterns has zero line-end corners in the square area and the linewidth standard deviation StdWidth is between 0 and 0.006, and wherein the second type of wafer circuit patterns is not measurable automatically by the electron beam linewidth defect scanning machine;
step 3: for the first type of wafer circuit patterns, performing automatic measurement by using the electron beam linewidth defect scanning machine; for the second type of wafer circuit patterns, first aligning the user designed circuit patterns manually with the second type of wafer circuit patterns, then performing measurement twice on the second type of wafer circuit patterns by the electron beam linewidth defect scanning machine to obtain two groups of measurement results;
step 4: reviewing the two groups of measurement results for the second type of wafer circuit patterns to determine if there is a measurement error; if there is a measurement error, repeat step 3 on the second type of wafer circuit patterns with the measurement error; if there is no measurement error, continue to step 5; and
step 5: analyzing the measurement results.”
Under the Step 1 of the eligibility analysis, we determine whether the claim is directed to a statutory category by considering whether the claimed subject matter falls within the four statutory categories of patentable subject matter identified by 35 U.S.C. 101: Process, machine, manufacture, or composition of matter. The above claim is considered to be in a statutory category (process for claim 1).
Under the Step 2A, Prong One, we consider whether the claim recites a judicial exception (abstract idea). In the above claim, the bold type portion constitutes an abstract idea because, under a broadest reasonable interpretation, it recites limitations that fall into/recite an abstract idea exceptions. Specifically, under the 2019 Revised Patent Subject matter Eligibility Guidance, it falls into the grouping of subject matter when recited as such in a claim that covers mental processes (concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions).
In claim 1, the steps identified in bold type are mental processes, therefore, they are considered to be abstract idea.
Next, under the Step 2A, Prong Two, we consider whether the claim that recites a judicial exception is integrated into a practical application.
In this step, we evaluate whether the claim recites additional elements that integrate the exception into a practical application of that exception.
The claim comprises the following additional elements:
providing wafer circuit patterns to be measured by an electron beam linewidth defect scanning machine, wherein the wafer circuit patterns are transferred from user designed circuit patterns onto a wafer by a semiconductor process, wherein the user designed circuit patterns may comprise line-end corners, and wherein the electron beam linewidth defect scanning machine has an electron beam scanning range which is a square area, wherein the square area has a side length; defining rules; three scenarios: in a first scenario, a number of the line-end corners is more than 0 in the square area; in a second scenario, the number of the line-end corners in the square area is 0 and a linewidth standard deviation StdWidth equals to 0; in a third scenario, the number of the line-end corners in the square area is 0 and the linewidth standard deviation StdWidth is equal to or greater than 0.006, wherein the first type of wafer circuit patterns is measurable automatically by the electron beam linewidth defect scanning machine, and wherein the second type of wafer circuit patterns has zero line-end corners in the square area and the linewidth standard deviation StdWidth is between 0 and 0.006, and wherein the second type of wafer circuit patterns is not measurable automatically by the electron beam linewidth defect scanning machine; for the first type of wafer circuit patterns, performing automatic measurement by using the electron beam linewidth defect scanning machine; for the second type of wafer circuit patterns; if there is a measurement error, repeat step 3 on the second type of wafer circuit patterns with the measurement error; if there is no measurement error; and step 5: analyzing the measurement results.
The additional elements “providing wafer circuit patterns to be measured by an electron beam linewidth defect scanning machine, wherein the wafer circuit patterns are transferred from user designed circuit patterns onto a wafer by a semiconductor process, wherein the user designed circuit patterns may comprise line-end corners, and wherein the electron beam linewidth defect scanning machine has an electron beam scanning range which is a square area, wherein the square area has a side length”; “defining rules”; “three scenarios: in a first scenario, a number of the line-end corners is more than 0 in the square area; in a second scenario, the number of the line-end corners in the square area is 0 and a linewidth standard deviation StdWidth equals to 0; in a third scenario, the number of the line-end corners in the square area is 0 and the linewidth standard deviation StdWidth is equal to or greater than 0.006, wherein the first type of wafer circuit patterns is measurable automatically by the electron beam linewidth defect scanning machine, and wherein the second type of wafer circuit patterns has zero line-end corners in the square area and the linewidth standard deviation StdWidth is between 0 and 0.006, and wherein the second type of wafer circuit patterns is not measurable automatically by the electron beam linewidth defect scanning machine”; “for the second type of wafer circuit patterns”; “if there is a measurement error, repeat step 3 on the second type of wafer circuit patterns with the measurement error; if there is no measurement error; and analyzing the measurement results” are not sufficient to integrate the abstract idea into a practical application because they only add insignificant extra-solution activities to the judicial exception. The additional element “for the first type of wafer circuit patterns, performing automatic measurement by the electron beam linewidth defect scanning machine” represents necessary data gathering and does not integrate the limitation into a practical application.
In conclusion, the above additional elements, considered individually and in combination with the other claims elements do not reflect an improvement to other technology or technical field, do not reflect improvements to the functioning of the computer itself, do not recite a particular machine, do not effect a transformation or reduction of a particular article to a different state or thing, and, therefore, do not integrate the judicial exception into a practical application. Therefore, the claim is directed to a judicial exception and require further analysis under the Step 2B.
The above claim, does not include additional elements that are sufficient to amount to significantly more than the judicial exception because they are generically recited and are well-understood/conventional in a relevant art as evidenced by the prior art of record (Step 2B analysis).
For example, for the first type of wafer circuit patterns, performing automatic measurement by the electron beam linewidth defect scanning machine is considered necessary data gathering. As recited in MPEP section 2106.05(g), necessary data gathering (i.e., obtaining measurement data) is considered extra solution activity in light of Mayo, 566 U.S. at 79, 101 USPQ2d at 1968; OIP Techs., Inc. v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1092-93 (Fed. Cir. 2015).
For example, wherein the first type of wafer circuit patterns is measurable automatically by the electron beam linewidth defect scanning machine is disclosed by “Yamaguchi US 20010019109”, [0002], [0004], [0005], [0012], [0060]; and “Taichi CN 112578631A”, Abstract, [0015], [0104], [0110].
The claim, therefore, is not patent eligible.
With regards to the dependent claims, claims 2-5, and 8 provide additional features/steps which are considered part of an expanded abstract idea of the independent claims, and do not integrate the abstract ideas into a practical application.
The dependent claims are, therefore, also not patent eligible.
Examiner' s Note
Regarding Claims 1-5, and 8, the most pertinent prior arts are “Yamaguchi US 20010019109”, “Taichi CN 112578631A”, “Sugiyama US 20080037830”, “Miyamoto US 20060284081”, “Sugiyama US 20110150345”, and “Fukaya US 20110139981”.
As to claims 1, Yamaguchi teaches “ providing wafer circuit patterns to be measured (Yamaguchi, [0002], [0012]);
defining rules to classify the wafer circuit patterns to be measured into a first type of wafer circuit patterns and a second type of wafer circuit patterns, where the first type of wafer circuit patterns are easily measurable with an electron beam linewidth defect scanning machine (Yamaguchi, [0002], [0004], [0005], [0012], [0060]), and wherein the second type of wafer circuit patterns are not easily measurable with the electron beam linewidth defect scanning machine (Yamaguchi, [0015], [0033], [0060]);
for the first type of wafer circuit patterns, performing automatic measurement by the electron beam linewidth defect scanning machine (Yamaguchi, [0002], [0004], [0005], [0012], [0060]);
if there is no measurement error, analyzing measurement results (Yamaguchi, [0014], [0015], [0059], [0060], [0062], [0063], [0071]).
Fukaya teaches providing wafer circuit patterns to be measured by an electron beam linewidth defect scanning machine (Fukaya, [0002], [0013]).
However, the prior arts of record, alone or in combination, do not fairly teach or suggest “providing wafer circuit patterns to be measured by an electron beam linewidth defect scanning machine, wherein the wafer circuit patterns are transferred from user designed circuit patterns onto a wafer by a semiconductor process, wherein the user designed circuit patterns may comprise line-end corners, and wherein the electron beam linewidth defect scanning machine has an electron beam scanning range which is a square area, wherein the square area has a side length”;
“defining rules to classify the wafer circuit patterns to be measured into a first type of wafer circuit patterns and a second type of wafer circuit patterns, wherein the first type of wafer circuit patterns comprises three scenarios: in a first scenario, a number of the line-end corners is more than 0 in the square area; in a second scenario, the number of the line-end corners in the square area is 0 and a linewidth standard deviation StdWidth equals to 0; in a third scenario, the number of the line-end corners in the square area is 0 and the linewidth standard deviation StdWidth is equal to or greater than 0.006, wherein the first type of wafer circuit patterns is measurable automatically by the electron beam linewidth defect scanning machine, and wherein the second type of wafer circuit patterns has zero line-end corners in the square area and the linewidth standard deviation StdWidth is between 0 and 0.006, and wherein the second type of wafer circuit patterns is not measurable automatically by the electron beam linewidth defect scanning machine”;
“for the first type of wafer circuit patterns, performing automatic measurement by using the electron beam linewidth defect scanning machine; for the second type of wafer circuit patterns, first aligning the user designed circuit patterns manually with the second type of wafer circuit patterns, then performing measurement twice on the second type of wafer circuit patterns by the electron beam linewidth defect scanning machine to obtain two groups of measurement results”;
“reviewing the two groups of measurement results for the second type of wafer circuit patterns to determine if there is a measurement error; if there is a measurement error, repeat step 3 on the second type of wafer circuit patterns with the measurement error; if there is no measurement error” including all limitations as claimed.
Dependent claims 2-5, and 8 are also distinguished over the prior art for at least the same reason as claim 1.
Examiner notes, however, that claims 1-5, and 8 are rejected under 35 U.S.C. 101, and therefore, not patent eligible.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAL CE MANG whose telephone number is (571)272-0370. The examiner can normally be reached Monday to Friday- 8:30-12:00, 1:00-5:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine T Rastovski can be reached at (571) 270-0349. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAL CE MANG/Primary Examiner, Art Unit 2857
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