Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
As to claim 1, the claim recites “A method for reducing measurement errors of critical pattern dimensions of polycrystal layers, at least comprising:
step 1: providing wafer circuit patterns to be measured;
step 2: defining rules to classify the wafer circuit patterns to be measured into a first type of wafer circuit patterns and a second type of wafer circuit patterns, where the first type of wafer circuit patterns are easily measurable with an electron beam linewidth defect scanning machine, and wherein the second type of wafer circuit patterns are not easily measurable with the electron beam linewidth defect scanning machine;
step 3: for the first type of wafer circuit patterns, performing automatic measurement by the electron beam linewidth defect scanning machine; for the second type of wafer circuit patterns, aligning user designed wafer circuit patterns manually with the second type of wafer circuit patterns before performing measurement by the electron beam linewidth defect scanning machine, and repeating the measurement to obtain two groups of measurement results;
step 4: reviewing the two groups of measurement results for the second type of wafer circuit patterns to determine if there is a measurement error; if there is a measurement error, repeat step 3 on the second type of wafer circuit patterns with the measurement error; if there is no measurement error, continue to step 5; and
step 5: analyzing the measurement results”.
Under the Step 1 of the eligibility analysis, we determine whether the claim is directed to a statutory category by considering whether the claimed subject matter falls within the four statutory categories of patentable subject matter identified by 35 U.S.C. 101: Process, machine, manufacture, or composition of matter. The above claim is considered to be in a statutory category (process for claim 1).
Under the Step 2A, Prong One, we consider whether the claim recites a judicial exception (abstract idea). In the above claim, the bold type portion constitutes an abstract idea because, under a broadest reasonable interpretation, it recites limitations that fall into/recite an abstract idea exceptions. Specifically, under the 2019 Revised Patent Subject matter Eligibility Guidance, it falls into the grouping of subject matter when recited as such in a claim that covers mental processes (concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions).
In claim 1, the steps identified in bold type are mental processes, therefore, they are considered to be abstract idea.
Next, under the Step 2A, Prong Two, we consider whether the claim that recites a judicial exception is integrated into a practical application.
In this step, we evaluate whether the claim recites additional elements that integrate the exception into a practical application of that exception.
The claim comprises the following additional elements:
providing wafer circuit patterns to be measured; defining rules; where the first type of wafer circuit patterns are easily measurable with an electron beam linewidth defect scanning machine, and wherein the second type of wafer circuit patterns are not easily measurable with the electron beam linewidth defect scanning machine; for the first type of wafer circuit patterns, performing automatic measurement by the electron beam linewidth defect scanning machine; the second type of wafer circuit patterns; repeating the measurement to obtain two groups of measurement results; if there is a measurement error, perform measurement by the electron beam linewidth defect scanning machine
on the second type of wafer circuit patterns with the measurement error; and if there is no measurement error, analyzing the measurement results.
The additional element “for the first type of wafer circuit patterns, performing automatic measurement by the electron beam linewidth defect scanning machine” represents necessary data gathering and does not integrate the limitation into a practical application.
The additional elements “providing wafer circuit patterns to be measured”; “defining rules”; “where the first type of wafer circuit patterns are easily measurable with an electron beam linewidth defect scanning machine”, and “wherein the second type of wafer circuit patterns are not easily measurable with the electron beam linewidth defect scanning machine”; “the second type of wafer circuit patterns”; “repeating the measurement to obtain two groups of measurement results”; “if there is a measurement error, perform measurement by the electron beam linewidth defect scanning machine on the second type of wafer circuit patterns with the measurement error”; and “if there is no measurement error, analyzing the measurement results” are not sufficient to integrate the abstract idea into a practical application because they only add insignificant extra-solution activities to the judicial exception.
In conclusion, the above additional elements, considered individually and in combination with the other claims elements do not reflect an improvement to other technology or technical field, do not reflect improvements to the functioning of the computer itself, do not recite a particular machine, do not effect a transformation or reduction of a particular article to a different state or thing, and, therefore, do not integrate the judicial exception into a practical application. Therefore, the claim is directed to a judicial exception and require further analysis under the Step 2B.
The above claim, does not include additional elements that are sufficient to amount to significantly more than the judicial exception because they are generically recited and are well-understood/conventional in a relevant art as evidenced by the prior art of record (Step 2B analysis).
For example, for the first type of wafer circuit patterns, performing automatic measurement by the electron beam linewidth defect scanning machine is considered necessary data gathering. As recited in MPEP section 2106.05(g), necessary data gathering (i.e., obtaining measurement data) is considered extra solution activity in light of Mayo, 566 U.S. at 79, 101 USPQ2d at 1968; OIP Techs., Inc. v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1092-93 (Fed. Cir. 2015).
For example, the first type of wafer circuit patterns are easily measurable with an electron beam linewidth defect scanning machine is disclosed by “Yamaguchi US 20010019109”, 0002], [0004], [0005], [0012], [0060]; and “Taichi CN 112578631A”, Abstract, [0015], [0104], [0110].
The claim, therefore, is not patent eligible.
With regards to the dependent claims, claims 2-8 provide additional features/steps which are considered part of an expanded abstract idea of the independent claims, and do not integrate the abstract ideas into a practical application.
The dependent claims are, therefore, also not patent eligible.
Examiner' s Note
Regarding Claims 1-8, the most pertinent prior arts are “Yamaguchi US 20010019109”, “Taichi CN 112578631A”, “Sugiyama US 20080037830”, “Miyamoto US 20060284081”, and “Sugiyama US 20110150345”.
As to claims 1, Yamaguchi teaches “ providing wafer circuit patterns to be measured (Yamaguchi, [0002], [0012]);
defining rules to classify the wafer circuit patterns to be measured into a first type of wafer circuit patterns and a second type of wafer circuit patterns, where the first type of wafer circuit patterns are easily measurable with an electron beam linewidth defect scanning machine (Yamaguchi, [0002], [0004], [0005], [0012], [0060]), and wherein the second type of wafer circuit patterns are not easily measurable with the electron beam linewidth defect scanning machine (Yamaguchi, [0015], [0033], [0060]);
for the first type of wafer circuit patterns, performing automatic measurement by the electron beam linewidth defect scanning machine (Yamaguchi, [0002], [0004], [0005], [0012], [0060]);
if there is no measurement error, analyzing the measurement results (Yamaguchi, [0014], [0015], [0059], [0060], [0062], [0063], [0071]).
However, the prior arts of record, alone or in combination, do not fairly teach or suggest for the second type of wafer circuit patterns, aligning user designed wafer circuit patterns manually with the second type of wafer circuit patterns before performing measurement by the electron beam linewidth defect scanning machine, and repeating the measurement to obtain two groups of measurement results;
reviewing the two groups of measurement results for the second type of wafer circuit patterns to determine if there is a measurement error; if there is a measurement error, performing measurement by the electron beam linewidth defect scanning machine on the second type of wafer circuit patterns with the measurement error; if there is no measurement error including all limitations as claimed.
Dependent claims 2-8 are also distinguish over the prior art for at least the same reason as claim 1.
Examiner notes, however, that claims 1-8 are rejected under 35 U.S.C. 101, and therefore, not patent eligible.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
“Miyamoto US 20070210252 ” teaches “(1) part or all of the number, coordinates and size/shape and imaging sequence of imaging points each for observation, the imaging position change method and imaging conditions can be calculated automatically from CAD data, (2) a combination of input information and output information for imaging recipe creation can be set arbitrarily, and (3) decision is made of imaging or processing at an arbitrary imaging point as to whether to be successful/unsuccessful and in case a failure is determined, a relief process can be conducted in which the imaging point or imaging sequence is changed.”
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/LAL CE MANG/Examiner, Art Unit 2857
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