Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the application filed on 04/24/2024. Currently claims 1-20 are pending in the application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being anticipated by claims 1-20 of U.S. Patent No. US 11171209 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because: Claims 1-20 of this application recite method steps and the composition of the layers that are recited in different claims of U.S. Patent No. US 11171209 B2.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al (US 20160027918 A1).
Regarding claim 1, Figures 1-5 of KIM disclose a method comprising:
forming a gate stack (220, [0051], Figure 1) over a fin (AF, please see Figure 10) that extends from a substrate (110, [0049]);
forming a first recess (350, [0083], please see Figure 10) in the fin adjacent the gate stack;
forming a source/drain region (180, [0048]) in the first recess, wherein forming the source/drain region comprises:
epitaxially growing a first semiconductor material (182, [0056) in the first recess, the first semiconductor material comprising doped silicon germanium;
epitaxially growing a second semiconductor material (184, [0056]) over the first semiconductor material, the second semiconductor material comprising doped silicon germanium and having a different composition than the first semiconductor material; and
selectively depositing a third semiconductor material (186, [0056]) over the second semiconductor material, the third semiconductor material comprising doped silicon germanium and having a different composition than the second semiconductor material; and
forming a source/drain contact in contact (240, [0059]) with the source/drain region.
Regarding claim 2, Figures 1-5 of KIM disclose that the method of claim 1, wherein forming the source/drain region further comprises: conformally depositing a fourth semiconductor material (188, [0056]) over the third semiconductor material, the fourth semiconductor material comprising doped silicon germanium and having a different composition than the third semiconductor material.
Regarding claim 3, Figures 1-5 of KIM disclose that the method of claim 2, wherein the first (182, [0056]), the second (184), the third (186), and the fourth (188) semiconductor materials comprise facets, and wherein a topmost point of the first semiconductor material is lower than a bottommost point of the third semiconductor material and a bottommost point of the fourth semiconductor material (Figure 1 teaches that the topmost point of 182 is lower than a bottommost point of 186 and 188).
Regarding claim 4, Figures 1-5 of KIM disclose that the method of claim 2, wherein forming the source/drain contact (240) comprises etching a second recess extending through the fourth semiconductor material and exposing the third semiconductor material (please see Figure 3B for etching to form a recess for 240 and 230, [0062]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-10 and 13-15 are rejected under 35 U.S.C. 103 as being obvious over KIM et al (US 20170154990 A1).
Regarding claims 5-6, Figures 1-5 of KIM do not explicitly teach that the method of claim 1, wherein selectively depositing the third semiconductor material comprises forming the third semiconductor material at a first process temperature, wherein epitaxially growing the first semiconductor material comprises forming the first semiconductor material at a second process temperature, and wherein the first process temperature is lower than the second process temperature, wherein the first process temperature is in a range from 300° C. to 600° C., and the second process temperature is in a range from 600° C. to 800° C.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to form a source/drain region with improved composition for best performance with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claims 7-8, Figures 1-5 of KIM do not explicitly teach that the method of claim 1, wherein the first semiconductor material has a dopant ion concentration of less than 5×10.sup.20 atoms/cm.sup.3, and the second semiconductor material has a dopant ion concentration of greater than 6×10.sup.20 atoms/cm.sup.3. Or
The method of claim 1, wherein the third semiconductor material has a dopant ion concentration of greater than 8×10.sup.20 atoms/cm.sup.3.
However, KIM teaches that the silicon germanium epitaxial layer 180 may be doped with a p-type impurity at a high concentration and may form at least portions of the source region and the drain region. The doping of the p-type impurity at a high concentration may be performed using an in-situ doping method where p-type impurity dopant atoms are introduced during the growth of the silicon germanium epitaxial layer 180. In other examples, the doping of the p-type impurity at a high concentration may be performed through an ion implantation process, using, as a buffer layer, the silicon capping layer 190 formed on the silicon germanium epitaxial layer 180 after the growth of the silicon germanium epitaxial layer 180 is completed. The concentration of the p-type impurity within the silicon germanium epitaxial layer 180 may be varied in proportion to the germanium (Ge) concentration, and for example, the second epitaxial layer 186 may have the highest concentration of the p-type impurity. In an example embodiment, the p-type impurity may be boron (B) ([0057]).
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to form a source/drain region with improved composition for best performance with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 9, Figures 1-5 of KIM disclose a method comprising:
etching a semiconductor fin (AF, [0106], please see Figure 10) to form a recess (350, [0101]) in the semiconductor fin;
forming a source/drain region (180, in Figure 1, SR/DR, [0077]) in the recess, wherein forming the source/drain region comprises:
epitaxially growing a first source/drain layer (considering a layer according to Figure 5 wherein the Ge concentration is 30 to 40 as the first source/drain layer) in the recess for a first period of time (layers are formed gradually and each layer requires a certain period of time to grow), the first source/drain layer having a germanium concentration of 30 to 40 atomic percent;
epitaxially growing a second source/drain layer in the recess for a second period of time, wherein epitaxially growing the second source/drain layer comprises forming the second source/drain layer over the first source/drain layer, the second source/drain layer having a germanium concentration of 40 to 50 atomic percent (considering a layer according to Figure 5 wherein the Ge concentration is 40 to 50 as a second source/drain layer that requires a certain period of time); and
depositing a third source/drain layer in the recess over the second source/drain layer, the third source/drain layer having a germanium concentration of 60 to 80 atomic percent (considering a layer according to Figure 5 wherein the Ge concentration is 60 to 80 as a third source/drain layer that requires a certain period of time);
forming an inter-layer dielectric (200, [0048]) over the source/drain region; and
forming a source/drain contact (240+230, [0048]) extending through the inter-layer dielectric to contact the source/drain region.
KIM does not explicitly teach that wherein the second period of time is greater than the first period of time.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use a time period as claimed in order to form a high quality layer for best performance with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 10, Figures 1-5 of KIM do not explicitly teach that the method of claim 9, wherein the first period of time is in a range from 10 seconds to 200 seconds, and the second period of time is in a range from 100 seconds to 600 seconds.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to form a source/drain region with improved composition with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 13, Figures 1-5 of KIM disclose that the method of claim 9, wherein forming the source/drain region (180) further comprises: depositing a fourth source/drain layer in the recess over the third source/drain layer, the fourth source/drain layer having a germanium concentration of less than 40 atomic percent (considering a layer at the top with germanium concentration of less than 40 atomic percent as the fourth layer according to Figure 5C) .
Regarding claim 14, Figures 1-5 of KIM disclose that the method of claim 13, wherein the source/drain contact is in physical contact with a top surface of the third source/drain layer (considering layer 186 includes third source/drain layer wherein contact 220+230 is in contact with 186 in Figure 3D).
Regarding claim 15, Figures 1-5 of KIM does not explicitly teach that the method of claim 9, wherein the first source/drain layer comprises a thickness that is in a range from of 1 nm to 10 nm, and the second source/drain layer comprises a thickness that is less than 25 nm.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to form a source/drain region with improved composition with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 16-20 are allowable.
Claims 11-12 are objected to as being dependent upon rejected base claims above, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and further overcoming the double patent rejections above.
Regarding claim 11, there is no prior art available nor obvious motivation to combine elements of prior art which teaches that the method of claim 10, wherein depositing the third source/drain layer in the recess is performed for a third period of time, wherein the third period of time is greater than the first period of time, and wherein the third period of time is shorter than the second period of time in combination with other limitation of the claim it depends.
Regarding claim 12, this claim is allowed as it depends on an allowed claim.
Regarding claim 16, there is no prior art available nor obvious motivation to combine elements of prior art which teaches a method, comprising: “forming a source/drain region in the opening, wherein forming the source/drain region comprises: epitaxially growing a first semiconductor material in the opening, wherein the first semiconductor material has a dopant concentration of less than 5×10.sup.20 atoms/cm.sup.3; epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material having a dopant concentration greater than 6×10.sup.20 atoms/cm.sup.3; and depositing a third semiconductor material over the second semiconductor material, the third semiconductor material having a dopant concentration greater than 8×10.sup.20 atoms/cm.sup.3, wherein after depositing the third semiconductor material, a first angle between intersecting facets at a top surface of the third semiconductor material is smaller than 90 degrees and larger than a second angle between intersecting facets at a top surface of the second semiconductor material, wherein the first angle is higher than and overlaps the second angle” in combination with other limitations in the claim.
Regarding claims 17-20, these claims are allowed as they depend on an allowed claim.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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