Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 14-17 and 19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lee et al. (US Pat. Pub. 2018/0033727).
Regarding claim 1, Lee teaches a semiconductor structure, comprising:
a substrate [fig. 13, substrate 10a and 10b];
a liner layer arranged along a sidewall of the substrate within a cross-sectional view [fig. 13, liner layer 20];
a conductive 2D material arranged on the liner layer within the cross-sectional view, wherein the conductive 2D material comprises a top surface that is above a top surface of the liner layer [fig. 13, 40 above 20, paragraph [0024] teaches 40 is 2D conductive material]; and
a conductive structure continuously extending from above the top surface of the conductive 2D material to below a bottom of the conductive 2D material, the conductive 2D material and the liner layer laterally separating the substrate from the conductive structure [fig. 13, 60/35 extending above the top surface of 40 and below the bottom of 40, 20 and 40 laterally separating 60/35 from 10b].
Regarding claim 2, Lee discloses the semiconductor structure of claim 1, wherein the conductive structure comprises a horizontally extending ledge protruding outward from a sidewall of the conductive structure, the conductive 2D material being arranged on the horizontally extending ledge of the conductive structure [fig. 13, reinterpreting the conductive structure to be 60, 35 and 30, a horizontal ledge being the top of 30 extending from a sidewall of 60/35, 40 being on top of the ledge of 30].
Regarding claim 3, Lee teaches the semiconductor structure of claim 2, wherein the conductive 2D material extends from a sidewall of the conductive structure to an outermost edge of the horizontally extending ledge of the conductive structure [fig. 13, 40 extends from a sidewall of 60/35 to an outermost edge of 30].
Regarding claim 4, Lee discloses semiconductor structure of claim 2, wherein the conductive structure comprises a second horizontally extending ledge protruding outward from a second sidewall of the conductive structure opposing the sidewall within the cross-sectional view, the conductive 2D material being also arranged on the second horizontally extending ledge of the conductive structure [fig. 13, 30 has a ledge extending on both sides of 60/35, layer 40 is on both ledges].
Regarding claim 5, Lee teaches the semiconductor structure of claim 1, wherein the conductive structure has a first width below the conductive 2D material, a second width directly between sidewalls of the conductive 2D material, and a third width over a top of the conductive 2D material, the first width and the third width being larger than the second width [fig. 13, 30 has a first width, 60/35 between 40 has a second width, 60/35 above 40 has a third width, the first and third widths wider than the second].
Regarding claim 7, Lee discloses the semiconductor structure of claim 1, wherein the substrate includes a dielectric disposed over a semiconductor body [fig. 1, semiconductor body 1, dielectric 10 which is 10a and 10b of fig. 13].
Regarding claim 14, Lee teaches a semiconductor structure, comprising:
a substrate [fig. 13, 10a, 10b, 45 and 50];
a liner layer laterally surrounded by the substrate [fig. 13, liner layer 20 surrounding by 10b];
a conductive 2D material laterally surrounded by the substrate, wherein the conductive 2D material is arranged on a top surface of the liner layer [fig. 13, 40 above 20, paragraph [0024] teaches 40 is 2D conductive material, layer 45 surrounds 40]; and
a conductive structure continuously extending from above the conductive 2D material to below the conductive 2D material, wherein the conductive structure has greater widths above and below the conductive 2D material than directly between sidewalls of the conductive 2D material [fig. 13, 60/35/30 extends above 40, below 40 and has greater widths above and below 40 than between sidewalls of 40].
Regarding claim 15, Lee discloses the semiconductor structure of claim 14, wherein the conductive 2D material does not have a dangling bond [paragraph [0024] teaches a graphene material, molybdenum sulfide, tungsten selenide among others that matches the materials used for the 2D material in applicants instant specification, paragraph [0021] of the specification, the same materials used in the same manner will have the same properties, therefore the conductive 2D material does not have a dangling bond].
Regarding claim 16, Lee teaches the semiconductor structure of claim 14, wherein the conductive 2D material is graphene [paragraph [0024]].
Regarding claim 17, Lee discloses the semiconductor structure of claim 14, wherein the conductive structure comprises a first horizontally extending surface and a second horizontally extending surface respectively protruding outward from a sidewall of the conductive structure above and below the conductive 2D material [fig. 13, conductive structure 60/35/30 has horizontally extending surfaces above and below 40, the top of 30 is below 40, the top of 35/60 is above 40].
Regarding claim 19, Lee teaches the semiconductor structure of claim 14, wherein the conductive structure has a topmost surface and a bottommost surface, the topmost surface having a first width continuously extending between opposing outermost edges of the topmost surface and the bottommost surface having a second width continuously extending between opposing outermost edges of the bottommost surface; and wherein the first width is larger than the second width [fig. 13, topmost surface of 60/35, bottommost surface of 30, the width of the top surface is greater than the width of the bottommost surface].
Allowable Subject Matter
Claims 8-13 are allowed.
Claims 6, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a conductive 2D material arranged along a sidewall of the liner layer and between the sidewalls of the substrate.
Conclusion
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/JOHN M PARKER/Primary Examiner, Art Unit 2899
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