DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/25/2024 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 8 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sung et al. (2020/0312976).
Re claim 1, Sung teaches a semiconductor device (Fig. 1) comprising: a first fin (110) extending in a first direction (X) over an upper surface of a substrate (101), wherein a first region (“left/right region”) of the first fin (110) is embedded in an isolation insulating layer (102); and a first epitaxial layer (116) disposed over the first region (“left/right region”) of the first fin (110), wherein a first interface between the first fin (110) and the first epitaxial layer (116) has a first portion (“left portion”), a second portion (“middle portion”), and a third portion (“right portion”) extending in order along a second direction (Y) perpendicular to the first direction (X), and wherein a level of the second portion (“middle portion”) is further away from the upper surface of the substrate (101) than a level of the first (“left portion”) and third (“right portion”) portions.
Re claim 5, Sung teaches the semiconductor device of claim 1, further comprising a first gate structure (160) disposed over a second region (“middle region”) of the first fin (110), wherein the second region (“middle region”) is adjacent the first region (“left/right region”).
Re claim 8, Sung teaches the semiconductor device of claim 5, wherein the first gate structure includes a gate electrode layer (160), gate dielectric layer (120), and gate sidewall spacers (150, 151).
Re claim 9, Sung teaches the semiconductor device of claim 8, wherein the first interface between the first fin (110) and the first epitaxial layer (116) laterally extends under the first gate structure (Fig. 1).
Claim(s) 11 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sung et al. (2020/0312976).
Re claim 11, Sung teaches a semiconductor device (Fig. 1) comprising: a fin (110) disposed over a substrate (101) extending along a first direction (X); and an epitaxial layer (116/118) disposed over a first region (“left/right region”) of the fin (110), wherein an interface between the epitaxial layer (116/118) and the first region (“left/right region”) of the fin (110) has a first portion (“left portion”), a second portion (“middle portion”), and third portion (“right portion”) in order along the first direction (X), wherein the first portion (“left portion”) and the third portion (“right portion”) have a first depth from an uppermost surface of the fin (110) and the second portion (“middle portion”) has a second depth from the uppermost surface of the substrate (101), and the second depth is less than the first depth (Fig. 1).
Prior art of record
Re claim 16, Sung et al. (2020/0312976) teaches a method of manufacturing a semiconductor device (Figs. 1-2), comprising: forming a plurality of fins (110) over a substrate (101), the plurality of fins extending in a first direction (X) and arranged in a second direction (Y) crossing the first direction (X); forming an isolation insulating layer (102) over the substrate (101) so that lower portions of the plurality of fins (110) are embedded in the isolation insulating layer (102) and upper portions of the plurality of fins are exposed from the isolation insulating layer (102). Sung does not explicitly teach recessing first regions of the plurality of fins to form recesses; and forming an epitaxial layer over each of the recesses, wherein in the recessing the first regions, a plasma etching operation is performed to form a first portion, a second portion, and third portion in order along the second direction, wherein the first portion and the third portion have a first depth from an uppermost surface of the fin and the second portion has a second depth from the uppermost surface of the substrate, and the second depth is less than the first depth.
Allowable Subject Matter
Claims 2-4, 6-7, 10 and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 2, Sung teaches the semiconductor device of claim 1, yet remains explicitly silent to further comprising a second fin extending in the first direction disposed over the upper surface of the substrate, wherein the second fin is spaced apart from the first fin in the second direction, a first region of the second fin is embedded in the isolation insulating layer; and a second epitaxial layer is disposed over the first region of the second fin.
Claims 3-4 are objected to for at least depending from objected claim 2.
Re claim 6, Sung teaches the semiconductor device of claim 5, yet remains explicitly silent to further comprising a second gate structure disposed over a third region of the first fin on an opposing side of the first region from the first gate structure.
Claim 7 is objected to for at least depending from objected claim 6.
Re claim 10, Sung teaches the semiconductor device of claim 1, yet remains explicitly silent to wherein the first fin is made of Si, and the first epitaxial layer includes SiP, SiC, or SiCP.
Re claim 12, Sung teaches the semiconductor device of claim 11, yet remains explicitly silent to wherein the first depth is in a range from 50 nm to 70 nm.
Re claim 13, Sung teaches the semiconductor device of claim 11, yet remains explicitly silent to wherein the second depth is in a range from 45 nm to 65 nm. Re claim 14, Sung teaches the semiconductor device of claim 11, yet remains explicitly silent to wherein a difference between the first depth and the second depth is in a range from 0.5 nm to 5 nm.
Re claim 15, Sung teaches the semiconductor device of claim 11, yet remains explicitly silent to wherein a ratio of the second depth to the first depth is in a range from 0.85 to 0.95.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not anticipate or make obvious the method of claim 16, including each of the limitations and specifically recessing first regions of the plurality of fins to form recesses; and forming an epitaxial layer over each of the recesses, wherein in the recessing the first regions, a plasma etching operation is performed to form a first portion, a second portion, and third portion in order along the second direction, wherein the first portion and the third portion have a first depth from an uppermost surface of the fin and the second portion has a second depth from the uppermost surface of the substrate, and the second depth is less than the first depth, for the same reasons as mentioned for claim 16 in the prior art of record above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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