Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18645747 filed on 04/25/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of claims 1-14, 21-26 in the reply filed on 07/19/2026 is acknowledged.
Allowable subject matter
Claims 3, 7, 9-10, 13, 23-26 are objected to as being dependent upon a rejected base claim (independent claims 1 & 8), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lin et al. (US 2023/0136541).
With respect to dependent claim 3, the cited prior art does not anticipate or make obvious, inter alia, the step of: “a passivation layer over the circuit substrate, wherein an opening is formed in the passivation layer and below the interconnect chip, and the dummy bars partially overlap the opening in a normal direction of the circuit substrate”.
With respect to dependent claim 7, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the dummy bars are laterally spaced apart from the conductive connectors”.
With respect to dependent claims 9-10, the cited prior art does not anticipate or make obvious, inter alia, the step of: “further comprising a passivation layer over the circuit substrate, the dummy bars are formed on the passivation layer and misaligned with the interconnect chip in a normal direction of the circuit substrate”.
With respect to dependent claim 13, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the interconnect chip has a first side and a second side opposite to the first side, and an amount of the dummy bars on the first side is different from an amount of the dummy bars on the second side”.
With respect to dependent claims 23-26, the cited prior art does not anticipate or make obvious, inter alia, the step of: “a second passivation layer formed on the circuit substrate, wherein the dummy bars are formed on the second passivation layer”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6, 8, 11-12, 14, 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2023/0136541).
Regarding independent claim 1, Lin et al. teach a package structure, comprising:
a circuit substrate (Fig. 2H, element 29, paragraph 0077);
a redistribution layer (Figs. 2D & 2H, element 201, paragraph 0061) over the circuit substrate;
an interconnect chip (Figs. 2C & 2H, element 2a, paragraph 0052) disposed between the circuit substrate and the redistribution layer;
a plurality of conductive connectors (Fig. 2H, element 23, paragraph 0047) around the interconnect chip;
a plurality of dummy bars (Fig. 2H, element 24, paragraph 0048 discloses element 24 comprising polyimide which is the same material as the instant application) between the interconnect chip and the conductive connectors, wherein the dummy bars are electrically insulated from the conductive connectors; and
an underfill (Fig. 2H, element 25, paragraph 0057-0058 disclose element 25 comprising dielectric material which is the same material as the instant application) disposed between the circuit substrate and the redistribution layer and encapsulating the interconnect chip, the dummy bars and the conductive connectors.
Regarding claim 2, Lin et al. teach wherein the dummy bars are formed on the redistribution layer and spaced apart from the circuit substrate (Fig. 2H).
Regarding claim 6, Lin et al. teach a plurality of semiconductor dies (Fig. 2H, elements 26, paragraph 0063) bonded to the redistribution layer, wherein the interconnect chip overlaps the semiconductor dies in a normal direction of the circuit
Regarding independent claim 8, Lin et al. teach a package structure, comprising:
a circuit substrate (Fig. 2H, element 29, paragraph 0077);
a redistribution layer (Figs. 2D & 2H, element 201, paragraph 0061) over the circuit substrate, wherein the redistribution layer comprises a first region (Fig. 2H, middle portion where elements 2a and 24 are located) and a second region (Fig. 2H, peripheral portion where elements 23 are located) outside the first region;
an interconnect chip (Figs. 2C & 2H, element 2a, paragraph 0052) disposed in the first region;
a plurality of dummy bars (Fig. 2H, element 24, paragraph 0048 discloses element 24 comprising polyimide which is the same material as the instant application) disposed in the first region and around the interconnect chip;
a plurality of conductive connectors (Fig. 2H, element 23, paragraph 0047) in the second region; and
an underfill (Fig. 2H, element 25, paragraph 0057-0058 disclose element 25 comprising dielectric material which is the same material as the instant application) disposed between the circuit substrate and the redistribution layer and encapsulating the interconnect chip, the dummy bars and the conductive connectors.
Regarding claim 11, Lin et al. teach wherein a distance between two adjacent dummy bars is less than a distance between two adjacent conductive connectors (Fig. 2H).
Regarding claim 12, Lin et al. teach wherein the dummy bars are located on each side of the interconnect chip (Fig. 2H).
Regarding claim 14, Lin et al. teach wherein the dummy bars comprise an insulation material (Fig. 2H, element 24, paragraph 0048 discloses element 24 comprising polyimide which is the same material as the instant application).
Regarding independent claim 21, Lin et al. teach a package structure, comprising:
a first passivation layer (Figs. 2D & 2H, dielectric layer directly below lowermost 201 and above 25) formed on a redistribution layer (Figs. 2D & 2H, RDL 201 located in outermost dielectric layer 200, paragraph 0061);
an interconnect chip (Figs. 2C & 2H, element 2a, paragraph 0052) bonded to the redistribution layer via a plurality of conductive features (Figs. 2C & 2H, lowermost RDL 201, paragraph 0052) through the first passivation layer;
a plurality of dummy bars (Fig. 2H, element 24, paragraph 0048 discloses element 24 comprising polyimide which is the same material as the instant application) formed on the first passivation layer;
a circuit substrate (Fig. 2H, element 29, paragraph 0077) electrically connected to the redistribution layer via a plurality of conductive connectors (Fig. 2H, element 23, paragraph 0047); and
an underfill (Fig. 2H, element 25, paragraph 0057-0058 disclose element 25 comprising dielectric material which is the same material as the instant application) disposed between the circuit substrate and the first passivation layer.
Regarding claim 22, Lin et al. teach wherein the underfill separates the interconnect chip from the dummy bars (Fig. 2H).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2023/0136541).
Regarding claim 4, Lin et al. teach wherein a ratio of a height of the conductive connectors to a height of the dummy bars is from 0.1 to 0.9 (Lin et al. teach different/varying heights of the conductive connectors, dummy bars, conductive traces etc. in Fig. 2H. Accordingly, the height is an art recognize variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the height and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed height is for a particular purpose that is critical to the overall claimed invention).
Regarding claim 5, Lin et al. teach wherein a ratio of a width of the conductive connectors to a width of the dummy bars is from 0.1 to 0.9 (paragraph 0055 discloses that the width of the conductors can vary. Accordingly, the width is an art recognize variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the width and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed width is for a particular purpose that is critical to the overall claimed invention).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
Prosecution Insights