DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schröder (United States Patent Application Publication No. US 2019/0074295 A1, hereinafter “Schröder”) and as further evidenced by Hatanpää et al. (United States Patent Application Publication No. US 2018/0099916 A1, hereinafter “Hatanpää”).
In reference to claim 1, Schröder discloses a method which meets the claim. Fig. 4 of Schröder discloses a method of fabricating a semiconductor device/memory cell transistor which comprises forming a ferroelectric dielectric material (8) over a semiconductor channel layer (4). A gate dielectric layer (6 - topmost) is deposited over the dielectric material (8). A metal gate electrode (10 – p. 2, paragraph 25) is formed over the gate dielectric layer (6 - topmost). Schröder discloses that the ferroelectric dielectric material (8) has a thickness from 2 nm to about 5000 nm. Hatanpää discloses that films with a thickness less than 10 nm are known as two-dimensional materials (p. 10, paragraph 142). Therefore the ferroelectric dielectric film (8) of Schröder is a two-dimensional material when having a thickness less than 10 nm. Schröder discloses (p. 4-5, paragraph 47) that a dipole is formed within the two-dimensional dielectric material (8).
With regard to claim 5, a buffer layer (6 – bottommost) is formed over the semiconductor channel layer (4) prior to forming the 2D dielectric material (8). The 2D dielectric material (8) is formed over the buffer layer (6 – bottommost).
In reference to claim 6, Schröder discloses (p. 4-5, paragraph 47) that the device undergoes an annealing process to crystallize the 2D dielectric material (8). It is understood that the buffer layer (6 – bottommost), made of a metal oxide (p. 3, paragraph 38), is crystallized during the annealing process.
With regard to claim 7, Schröder discloses (p. 4-5, paragraph 47) that the device undergoes an annealing process to crystallize the 2D dielectric material (8) which forms the dipole within the 2D dielectric material (8). Schröder discloses (p. 5, paragraph 48) that the annealing/dipole formation process takes place after forming the 2D dielectric material (8) and prior to the deposition of the gate dielectric layer (6 – topmost).
In reference to claim 9, the gate dielectric layer (6 – topmost) is made of hafnium oxide and tantalum oxide (p. 3, paragraphs 34 and 38). The applicant discloses that these are known high-K materials (p. 12, paragraph 33 of the currently filed specification). Thus Schröder meets the claim.
Claim 18 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schröder and as further evidenced by Hatanpää and as further evidenced by Yang et al. (United States Patent Application Publication No. US 2022/0254900 A1, hereinafter “Yang”).
In reference to claim 18, Schröder discloses a device which meets the claim. Fig. 4 of Schröder discloses a semiconductor device/memory cell transistor which comprises a ferroelectric dielectric material (8) over a semiconductor channel layer (4). Schröder discloses that the ferroelectric dielectric material (8) has a thickness from 2 nm to about 5000 nm. Hatanpää discloses that films with a thickness less than 10 nm are known as two-dimensional materials (p. 10, paragraph 142). Therefore the ferroelectric dielectric film (8) of Schröder is a two-dimensional material when having a thickness less than 10 nm. A gate dielectric layer (6 - topmost) is deposited over the dielectric material (8). The gate dielectric layer (6 – topmost) is made of hafnium oxide and tantalum oxide (p. 3, paragraphs 34 and 38). The applicant discloses that these are known high-K materials (p. 12, paragraph 33 of the currently filed specification). A metal gate electrode (10 – p. 2, paragraph 25) is formed over the gate dielectric layer (6 - topmost). Schröder discloses (p. 4-5, paragraph 47) that a dipole is formed within the two-dimensional dielectric material (8). Schröder further discloses that the ferroelectric dielectric material (8) is HfO2 doped with titanium (p. 3-4, paragraphs 38-40). Yang discloses that titanium induces a dipole in HfO2 (p. 3, paragraph 32). Thus Schroder meets the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Schröder and as further evidenced by Hatanpää as applied to claim 1 above and further in view of Saitoh et al. (United States Patent Application Publication No. US 2011/0303972 A1, hereinafter “Saitoh”).
In reference to claim 2, as noted in the above rejection of claim 1, fig. 4 of Schröder discloses a memory cell transistor with a gate stack which includes a 2D dielectric material (8) disposed over a semiconductor channel layer (4), a gate dielectric layer (6 - topmost) is deposited over the 2D dielectric material (8), and a metal gate electrode (10 – p. 2, paragraph 25) formed over the gate dielectric layer (6 - topmost).
Fig. 4 of Schröder does not disclose implementing a plurality of the memory cell transistors in a stacked device structure with a first device/memory cell transistor vertically stacked over a second device/ memory cell transistor, wherein the first and second devices/ memory cell transistors include respective first and second gate stacks, and wherein at least one of the first and second gate stacks includes the 2D dielectric material disposed over a respective semiconductor channel layer, the gate dielectric layer disposed over the 2D dielectric material, and the metal gate electrode disposed over the gate dielectric layer. However Saitoh discloses (p. 9, paragraph 152) that stacking one memory cell transistor over another memory cell transistor provides the benefit of allowing a higher number of devices/memory cell transistors in a substrate area. In view of Saitoh, it would therefore be obvious to implement a stacked device structure with the memory cell transistor of Schröder. The stacking method of Saitoh is the conventional semiconductor fabrication method in which layers of each level are directly deposited on each other to form a monolithic device. Thus in the method of Schröder constructed in view of Saitoh, the device structure is monolithically stacked.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Schröder and as further evidenced by Hatanpää as applied to claim 1 above and further in view of Saitoh and further in view of Or-Bach et al. (United States Patent Application Publication No. US 2011/0121366 A1, hereinafter “Or-Bach”).
In reference to claim 3, as noted in the above rejection of claim 1, fig. 4 of Schröder discloses a memory cell transistor with a gate stack which includes a 2D dielectric material (8) disposed over a semiconductor channel layer (4), a gate dielectric layer (6 - topmost) is deposited over the 2D dielectric material (8), and a metal gate electrode (10 – p. 2, paragraph 25) formed over the gate dielectric layer (6 - topmost).
Fig. 4 of Schröder does not disclose implementing a plurality of the memory cell transistors in a stacked device structure with a first device/memory cell transistor vertically stacked over a second device/memory cell transistor, wherein the first and second devices/memory cell transistors include respective first and second gate stacks, and wherein at least one of the first and second gate stacks includes the 2D dielectric material disposed over a respective semiconductor channel layer, the gate dielectric layer disposed over the 2D dielectric material, and the metal gate electrode disposed over the gate dielectric layer. However Saitoh discloses (p. 9, paragraph 152) that stacking one memory cell transistor over another memory cell transistor provides the benefit of allowing a higher number of devices/memory cell transistors in a substrate area. In view of Saitoh, it would therefore be obvious to implement a stacked device structure with the memory cell transistor of Schröder.
Saitoh does not disclose sequentially stacking separate prefabricated transistor layers on each other to form a sequential stacked device. However Or-Bach discloses that there is a limit to monolithically forming transistor layers on a substrate since producing more transistor layers risks the functional yield of the device (p. 6, paragraph 813). To avoid this problem, Or-Bach discloses sequentially stacking separate prefabricated transistor layers (p. 6, paragraph 813). In view of Or-Bach, it would therefore be obvious to implement the method of Schröder constructed in view of Saitoh by sequential stacking.
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Schröder and as further evidenced by Hatanpää as applied to claim 1 above and further in view of Tanaka et al. (United States Patent Application Publication No. US 2014/0070289 A1, hereinafter “Tanaka”).
In reference to claim 4, Schröder does not disclose that the 2D crystalline ferroelectric material (8) is made of a metal silicate (MSiOx). However Tanaka discloses the known use of hafnium silicate (HfSiOx) as a ferroelectric material (p. 1, paragraph 4). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to use a metal silicate in the form of hafnium silicate as the 2D crystalline ferroelectric material in the method of Schröder.
With regard to claim 8, the method of Schröder constructed in view of Tanaka uses a 2D dielectric material in the form of a metal silicate (p. 1, paragraph 4 of Tanaka). The applicant discloses that the formation of the metal silicate itself is the process of forming a dipole within the material during its formation (p. 27, paragraph 63 of the currently filed specification). Thus the method of Schröder constructed in view of Tanaka meets claim 8.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Schröder and as further evidenced by Hatanpää.
In reference to claim 10, Schröder discloses that the 2D dielectric material (8) is annealed in order to crystallize it at a temperature from about 400 to about 1200 degrees Celsius (p. 4, paragraph 45). Thus the 2D dielectric material (8) is deposited/formed in an amorphous state at a temperature below 400 degrees Celsius which overlaps the claimed range of 300-750 degrees Celsius. The examiner would like to note:
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05.
Thus claim 10 is not patentable over Schröder.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Schröder and as further evidenced by Hatanpää and as further evidenced by Yang as applied to claim 18 above and further in view of Tanaka.
In reference to claim 19, Schröder does not disclose that the 2D crystalline ferroelectric material (8) is made of a metal silicate (MSiOx). However Tanaka discloses the known use of hafnium silicate (HfSiOx) as a ferroelectric material (p. 1, paragraph 4). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to use a metal silicate in the form of hafnium silicate as the 2D crystalline ferroelectric material in the Schröder device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Schröder and as further evidenced by Hatanpää and as further evidenced by Yang as applied to claim 18 above and further in view of Saitoh.
In reference to claim 20, as noted in the above rejection of claim 18, fig. 4 of Schröder discloses a memory cell transistor with a gate stack which includes a 2D dielectric material (8) disposed over a semiconductor channel layer (4), a high-K gate dielectric layer (6 - topmost) is deposited over the 2D dielectric material (8), and a metal gate electrode (10 – p. 2, paragraph 25) formed over the high-K gate dielectric layer (6 - topmost).
Fig. 4 of Schröder does not disclose implementing a plurality of the memory cell transistors in a stacked device structure with a first device/memory cell transistor vertically stacked over a second device/ memory cell transistor, wherein the first and second devices/memory cell transistors include respective first and second gate stacks, and wherein at least one of the first and second gate stacks includes the 2D dielectric material disposed over a respective semiconductor channel layer, the high-K dielectric layer disposed over the 2D dielectric material, and the metal gate electrode disposed over the high-K dielectric layer. However Saitoh discloses (p. 9, paragraph 152) that stacking one memory cell transistor over another memory cell transistor provides the benefit of allowing a higher number of devices/memory cell transistors in a substrate area. In view of Saitoh, it would therefore be obvious to implement a stacked device structure with the memory cell transistor of Schröder.
Allowable Subject Matter
Claims 11-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a method which comprises forming a stacked device structure with first and second devices having respective first and second gate stacks that are formed by a channel release process which selectively removes a dummy layer from adjacent channel layers in combination with the step of forming a two-dimensional (2D) dielectric material (which has a dipole-inducing element) over the channel layers and depositing a high-K gate dielectric over the 2D dielectric material as specified by the applicant in claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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