DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, including claims 1-16 and 21-24 in the reply filed on June 30, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11, and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (2021/0375669, hereafter Liu).
Regarding claim 11, Liu discloses a semiconductor device, comprising: a substrate (108, Fig. 1A); a pixel structure (122A, Fig. 1A) comprising: an epitaxial structure (124, Fig. 1A) disposed in the substrate, wherein the epitaxial structure comprises a bottom surface (124 upper, Fig. 1B) with a first width and a top surface (124f, Fig. 1B) with a second width that is greater than the first width; and a capping layer (126, Fig. 1A), disposed on the epitaxial structure, comprising a band gap different from a band gap of a material of the epitaxial structure (par. 0031); and an isolation structure (102B, Fig. 1A) comprising a doped region (140, Fig. 1A, par. 0035) disposed adjacent to the pixel structure.
Regarding claim 13, Liu discloses a semiconductor device wherein the epitaxial structure (124) comprises a tapered structure (Fig. 1B).
Regarding claim 14, Liu discloses a semiconductor device wherein the epitaxial structure (124, Fig. 1B) comprises a layer of silicon, silicon germanium, or a group III-V element of the periodic table (par. 0030).
Regarding claim 15, Liu discloses a semiconductor device wherein the capping layer comprises a silicon-based material (par. 0031).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-10, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Lee et al. (2022/0123032, hereafter Lee) and Loh et al. (2011/0084308, hereafter Loh).
Regarding claim 1, Liu discloses a semiconductor device, comprising: a substrate (108, Fig.1A, par. 0023); a pixel region (102A, Fig. 1A, par. 0024) with a pixel structure (122A/122B, Fig. 1A, par. 0025), wherein the pixel structure comprises: an epitaxial structure, comprising: an embedded portion (124, Fig. 1A, par. 0029) and a capping layer (126, Fig. 1E, par. 0029); an isolation region (102B, Fig. 1A, par. 0024) with an isolation structure (140, Fig. 1A, par. 0037) disposed adjacent to the pixel region; and a contact pad region (102C, Fig. 1A, par. 0024) with a pad structure (120, Fig. 1A, par. 0025) disposed adjacent to the isolation region.
Liu fails to disclose an embedded portion with a stepped structure disposed in the substrate.
However, Lee teaches an embedded portion with a stepped structure disposed in the substrate (110(IR1), Fig. 6, par. 0054).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Lee by providing an embedded layer in the substrate that has a stepped structure in order to optimize channel strain design to boost carrier mobility while controlling parasitic capacitance.
Liu and Lee fail to disclose a protruding portion extending above a top surface of the substrate.
However, Loh teaches a protruding portion extending above a top surface of the substrate (112 top, Fig. 1, par. 0034).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu and Lee with Loh by providing a protruding portion in order to increase active channel area to lower electrical resistance and improve drive current while maintaining compactness.
Regarding claim 2, Liu fails to disclose a semiconductor device wherein the embedded portion comprises a sidewall with a stepped profile.
However, Lee teaches a semiconductor device wherein the embedded portion comprises a sidewall with a stepped profile.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Lee by providing an epitaxial structure with a stepped profile in order to optimize channel strain design to boost carrier mobility while controlling parasitic capacitance.
Regarding claim 3, Liu discloses a semiconductor device wherein the embedded portion (124) comprises: a bottom portion (124 upper) with a first width; and a top portion (124 lower) with a second width that is greater than the first width (Fig. 1B).
Regarding claim 4, Liu fails to disclose a semiconductor device wherein the embedded portion comprises: a bottom portion with a first width; and a top portion with a second width that is about 1.2 times of the first width.
However, Lee teaches a semiconductor device wherein the embedded portion (110(IR1), Fig. 6) comprises: a bottom portion (110(IR1) bottom) with a first width (W12); and a top portion (110(IR1) top) with a second width (W11) that is about 1.2 times of the first width (par. 0079).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Lee by providing a top portion with a width about 1.2 times greater than the bottom portion in order to increase landing area for contacts to reduce resistance, prevent current crowding at interface, and provide structural tolerance for misalignment.
Regarding claim 6, Liu fails to disclose a semiconductor device wherein the embedded portion comprises: a bottom portion with a first height; and a top portion with a second height that is less than the first height.
However, Lee teaches a semiconductor device wherein the embedded portion (110(IR1), Fig. 11) comprises: a bottom portion with a first height (H2); and a top portion with a second height (H3) that is less than the first height (par. 0128).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Lee by providing a top portion with a height that is less than the bottom portion in order to minimize parasitic capacitance with adjacent structures and prevent lattice strain relaxation while providing necessary depth.
Regarding claim 7, Liu fails to disclose a semiconductor device wherein the embedded portion comprises: a bottom portion with a first height; and a top portion with a second height that is about 25% of a sum of the first and second heights.
However, Lee teaches an embedded portion with bottom and top portions with different heights. A fixed ratio does not allow for dynamic targets considering channel strain optimization, contact resistance, and parasitic capacitance, and it does not allow for practical fabrication. Further, heights are determined independently to allow for an independently designed stress profile and contact area. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 8, Liu and Lee fail to disclose a semiconductor device wherein the protruding portion comprises: a substantially planar top surface; and a sidewall with a sloped profile.
However, Loh teaches a semiconductor device wherein the protruding portion (112 top, Fig. 1) comprises: a substantially planar top surface; and a sidewall with a sloped profile (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu and Lee with Loh by implementing a protruding portion with a planar surface and sloped sidewalls in order to provide a stable landing pad while relaxing interfacial stress and preventing electric field crowding.
Regarding claim 9, Liu and Lee fail to disclose a semiconductor device wherein the protruding portion comprises a sloped sidewall that forms an angle of about 5 degrees or less with a sidewall of the capping layer.
However, Loh teaches a protruding portion with a sloped sidewall. Low angles ignore the crystallographic growth habit of silicon, and such steep angles create stress. Further, such low angles are practically equivalent to a vertical structure and more prominent slopes are required for strain relief, defect-free growth, and reliable coverage. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 10, Liu discloses a semiconductor device wherein the pixel structure (122A, Fig. 1A) further comprises a doped region (130/132, Fig. 1A, par. 0029) disposed in the epitaxial structure (124, Fig. 1A) and the capping layer (126, Fig. 1A).
Regarding claim 23, Liu and Lee fail to disclose a semiconductor device wherein the epitaxial structure comprises a protruding portion extending above a top surface of the substrate, and wherein the protruding portion comprises a tapered cross-sectional profile.
However, Loh teaches a semiconductor device wherein the epitaxial structure (112) comprises a protruding portion extending above a top surface of the substrate (104), and wherein the protruding portion comprises a tapered cross-sectional profile (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu and Lee with Loh by providing a protruding portion with a tapered profile in order to relax mechanical stress and suppress electric field concentration near edges.
Regarding claim 24, Liu and Lee fail to disclose a semiconductor device wherein the epitaxial structure comprises: an embedded portion in the substrate; and a protruding portion extending above a top surface of the substrate.
However, Loh teaches a semiconductor device wherein the epitaxial structure (112) comprises: an embedded portion (112 lower) in the substrate; and a protruding portion (112 upper) extending above a top surface of the substrate (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu and Lee with Loh by providing an embedded and protruding portion in order to increase active channel area to lower electrical resistance and improve drive current while maintaining compactness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Lee and Loh as applied to claim 1 above, and further in view of Wei et al. (2015/0091065, hereafter Wei).
Regarding claim 5, Liu fails to disclose a semiconductor device wherein the embedded portion comprises: a top portion with a second width that is about 1.2 times of the first width.
However, Lee teaches a semiconductor device wherein the embedded portion (110(IR1), Fig. 6) comprises: a top portion with a second width (W11) that is about 1.2 times of the first width (W12).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Lee by providing a top portion with a width about 1.2 times the bottom portion in order to increase landing area for contacts to reduce resistance, prevent current crowding at interface, and provide structural tolerance for misalignment.
Liu, Lee, and Loh fail to disclose a bottom portion with a first width equal to or greater than about 0.5 microns.
However, Wei teaches a bottom portion with a first width equal to or greater than about 0.5 microns.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu, Lee, and Loh with Wei by providing a bottom portion with a width equal to or greater than about 0.5 microns in order to ensure photo-induced carriers pass through freely.
Claims 12 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Lee.
Regarding claim 12, Liu fails to disclose a semiconductor device wherein the epitaxial structure comprises a stepped structure.
However, Lee teaches a semiconductor device wherein the epitaxial structure (110(IR1)) comprises a stepped structure (Fig. 6).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Lee by providing an epitaxial structure that is stepped in order to optimize channel strain design to boost carrier mobility while controlling parasitic capacitance.
Regarding claim 21, Liu discloses a semiconductor device, comprising: a substrate (108, Fig. 1A); an epitaxial structure (122A, Fig. 1A), a capping layer (126, Fig. 1A) disposed on the epitaxial structure; a doped region (130/132, Fig. 1A) in the epitaxial structure and the capping layer; a silicide layer (134A, Fig. 1A, par. 0034) disposed on the doped region; an etch stop layer (116, Fig. 1A, par. 0024) disposed on the silicide layer; and a conductive plug (134B, Fig. 1A, par. 0034) disposed on the silicide layer through the etch stop layer.
Liu fails to disclose an epitaxial structure with a stepped cross-sectional profile disposed in the substrate.
However, Lee teaches an epitaxial structure with a stepped cross-sectional profile disposed in the substrate (110(IR1), Fig. 6).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Lee by providing an epitaxial structure that is stepped in order to optimize channel strain design to boost carrier mobility while controlling parasitic capacitance.
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Loh.
Regarding claim 16, Liu fails to disclose a semiconductor device wherein the top surface of the epitaxial structure comprises a first surface portion with a linear profile and a second surface portion with a curved profile.
However, Loh teaches a semiconductor device wherein the top surface of the epitaxial structure (112) comprises a first surface portion with a linear profile and a second surface portion with a curved profile (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu with Loh by providing an epitaxial structure surface with a both linear and curved portions in order to provide stable, low-resistance landing pad for contacts while relaxing mechanical stress and suppressing electric field concentration near edges.
Claims 22 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Lee as applied to claim 21 above, and further in view of Park (KR-20040103340, hereafter Park).
Regarding claim 22, Liu and Lee fail to disclose a semiconductor device wherein the epitaxial structure comprises: a bottom epitaxial structure with a first width; a middle epitaxial structure with a second width greater than the first width; and a top epitaxial structure with a third width greater than the first and second widths.
However, Park teaches a semiconductor device wherein the epitaxial structure (192, Fig. 7) comprises: a bottom epitaxial structure with a first width; a middle epitaxial structure with a second width greater than the first width; and a top epitaxial structure with a third width greater than the first and second widths (Fig. 7, par. 0064).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Liu and Lee with Park by providing a stepped structure with three different widths in order to provide multiple potentials when charges move such that accumulated charge is less than transfer voltage so that charges cannot move to the floating diffusion region.
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/C.M.B./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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