DETAILED ACTION
This Office action is in response to the amendment filed 21 October 2025. By this amendment, claims 1, 16, 21, and 27 are amended. Claims 1-8 and 16-27 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to amended claims 1, 16, and 21 have been considered but are moot because the grounds of rejection have been modified in response to Applicant’s amendments to the claims. The amended limitations are addressed by the modified grounds of rejection below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-8, and 16-27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by WO 2015/001987 A1 (PCT/JP2014/066400) to Masuda et al. (citations refer to US 2016/0112614 A1 as the English language equivalent; hereinafter “Masuda”).
Regarding independent claim 1, Masuda (Fig. 13) discloses a semiconductor device, comprising:
a plurality of photodiodes 42 (¶ 0142);
a semiconductor structure 41 (¶¶ 0126, 0054) overlapping the plurality of photodiodes, the semiconductor structure comprising a plurality of microstructures 48 (¶ 0132) on a backside (top of 41) of the semiconductor structure 41;
a dielectric layer 114 (¶ 0130; alternatively, 46, labelled in Fig. 11, ¶ 0061) over the plurality of microstructures of the semiconductor structure;
a color filter layer 51 (¶ 0129) over the dielectric layer 46, wherein a vertical distance from the color filter layer 51 to one of the plurality of microstructures 48 is less than a vertical distance from one of the plurality of photodiodes 42 to said one of the plurality of microstructures (vertical distance from 51 to the top of a tip of 48 is less than the vertical distance from 42 to that tip of 48); and
a micro-lens 52 (¶ 0129) over the color filter layer 51.
Regarding claim 2, Masuda (Fig. 13) discloses the semiconductor device of claim 1, wherein the plurality of microstructures 48 form a zigzag pattern in a cross-sectional view (Fig. 13).
Regarding claim 4, Masuda (Fig. 13) discloses the semiconductor device of claim 1, wherein the dielectric layer 46 forms an interface with the plurality of microstructures 48, and the interface has a zigzag pattern in a cross-sectional view (Fig. 13).
Regarding claim 5, Masuda (Fig. 13) discloses the semiconductor device of claim 1, wherein the plurality of microstructures 48 are formed of silicon (¶ 0054).
Regarding claim 6, Masuda (Fig. 13) discloses the semiconductor device of claim 1, wherein a thickness of the dielectric layer 114 is less than a thickness of the color filter layer 51 (Fig. 13).
Regarding claim 7, Masuda (Fig. 13) discloses the semiconductor device of claim 1, wherein each of the plurality of microstructures 48 has a pointed top from a cross-sectional view (Fig. 13).
Regarding claim 8, Masuda (Fig. 13) discloses the semiconductor device of claim 1, wherein the microstructures 48 continuously extend from the backside (top) of the semiconductor structure 41 (Fig. 13).
Regarding independent claim 16, Masuda (Fig. 15) discloses a semiconductor device, comprising:
a plurality of photo-sensing pixel regions 42 (¶¶ 0151, 0142);
a semiconductor region 41 (¶¶ 0126, 0054) covering the plurality of photo-sensing pixel regions, the semiconductor region comprising a plurality of microstructures 48 (¶ 0132) on a backside (top of 41) of the semiconductor region 41; and
a dielectric layer 112 (¶ 0130; alternatively 46, labelled in Fig. 11, ¶ 0061) over the plurality of microstructures 48 of the semiconductor region, wherein a thickness of the dielectric layer 112 is less than a vertical distance from the plurality of photo-sensing pixel regions 42 to the plurality of microstructures 48 (Fig. 15; alternatively, thickness of 46 as measured from a top tip of 48 to the top of 46 is less than a vertical distance from 42 to said top tip of 48), wherein a bottommost position of the dielectric layer 112 (or 46) is higher than a topmost position of the plurality of photo-sensing pixel regions 42 (Fig. 15).
Regarding claim 17, Masuda (Fig. 15) discloses the semiconductor device of claim 16, wherein the dielectric layer 46 has a zigzag surface (Fig. 15).
Regarding claim 18, Masuda (Fig. 15) discloses the semiconductor device of claim 17, wherein the zigzag surface of the dielectric layer 46 (labelled in Fig. 11) is in contact with the plurality of microstructures 48 (Fig. 15).
Regarding claim 19, Masuda (Fig. 15) discloses the semiconductor device of claim 17, wherein the dielectric layer 46 (labelled in Fig. 11) has a top surface (interfacing with 51) opposite the zigzag surface (bottom), and the top surface is more planar than the zigzag surface (Fig. 15).
Regarding claim 20, Masuda (Fig. 15) discloses the semiconductor device of claim 16, further comprising: a color filter layer 51 (¶ 0129) over the dielectric layer 112.
Regarding independent claim 21, Masuda (Fig. 15) discloses a semiconductor device, comprising: a plurality of photo-sensing regions 42 (¶¶ 0151, 0142);
a semiconductor structure 41 (¶¶ 0126,0054) over the plurality of photo-sensing regions, the semiconductor structure comprising a plurality of microstructures 48 (¶ 0132) on a backside (top of 41) of the semiconductor structure 41;
a dielectric layer 114 (¶ 0130; alternatively 46, labelled in Fig. 11, ¶ 0061) over the plurality of microstructures 48 of the semiconductor structure, wherein a thickness of the dielectric layer 114 is less than a vertical distance from one of the plurality of photo-sensing regions 42 to one of the plurality of microstructures 48 (Fig. 15; alternatively, thickness of 46 as measured from a top tip of 48 to the top of 46 is less than a vertical distance from 42 to said top tip of 48),
wherein an entirety of the dielectric layer 114 (or 46) is above top surfaces of the plurality of photo-sensing regions 42 (Fig. 15);
a color filter layer 51 (¶ 0129) over the dielectric layer; and
a micro-lens 52 (¶ 0129) over the color filter layer 51.
Regarding claim 22, Masuda (Fig. 15) discloses the semiconductor device of claim 21, wherein the dielectric layer 114 comprises silicon oxide, silicon nitride or silicon oxynitride (¶ 0130).
Regarding claim 23, Masuda (Fig. 15) discloses the semiconductor device of claim 21, wherein the dielectric layer 46 forms an interface with the plurality of microstructures 48 of the semiconductor structure, and an entirety of the interface is a zigzag pattern in a cross-sectional view (Fig. 15).
Regarding claim 24, Masuda discloses the semiconductor device of claim 21, wherein the plurality of microstructures 48 are formed of an epitaxial material. The limitation “formed of an epitaxial material” is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966. Here, Masuda discloses the plurality of microstructures 48 are formed of silicon (¶ 0054), a material that is known in the art to be capable of being formed by epitaxy.
Regarding claim 25, Masuda discloses the semiconductor device of claim 21, wherein the plurality of microstructures 48 are formed of silicon (¶ 0054).
Regarding claim 26, Masuda (Fig. 15) discloses the semiconductor device of claim 21, wherein the color filter layer 51 is in contact with the dielectric layer 46 (labelled in Fig. 11).
Regarding claim 27, Masuda (Fig. 15) discloses the semiconductor device of claim 21, wherein the micro-lens 52 have a width greater than a width of one of the plurality of microstructures 48 (Fig. 15).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Masuda as applied to claim 1 above, and further in view of US 2009/0286346 to Adkisson et al. (hereinafter “Adkisson”).
Regarding claim 3, Masuda discloses the semiconductor device of claim 1, wherein the microstructures have different shapes (e.g., Fig. 2, Fig. 13; ¶ 0056), however fails to expressly disclose the plurality of microstructures form trapezoidal patterns spaced apart from each other in a cross-sectional view. In the same field of endeavor, Adkisson (Fig. 1I) discloses a semiconductor device including a plurality of microstructures 101 (¶ 0095) forming trapezoidal patterns spaced apart from each other (Figs. 1D-1F; ¶ 0092), in a cross-sectional view (Fig. 1I). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use modify the semiconductor device of Masuda to include the microstructure shape as disclosed in Adkisson for the purpose of providing an art recognized alternative microstructure shape to provide an anti-reflective region and to enhance device performance (Adkisson, ¶ 0092).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
21 January 2026
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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