DETAILED ACTION
This Office action is in response to the RCE filed 24 April 2026. Claims 1, 4-8, 16-19, 21-30 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2 April 2026 has been entered.
Response to Arguments
Applicant's arguments filed 2 April 2026 have been fully considered but they are not persuasive; the rejections of the claims have been modified in response to Applicant's amendments to the claims. The amended limitations (and Applicant’s arguments regarding the amended limitations) are addressed by the modified rejections below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "the bottommost position" in lines 11-12 and “the topmost position” in line 12. There is insufficient antecedent basis for these limitations in the claim. For the purposes of examination, it is assumed --a bottommost position-- and --a topmost position-- were the intended recitations. Claims 17-19 depend from claim 16 and thus also contain the above indefinite language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-8, 16-19, 21-30 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2015/001987 A1 (PCT/JP2014/066400) to Masuda et al. (citations refer to US 2016/0112614 A1 as the English language equivalent; hereinafter “Masuda”) in view of US 2009/0286346 to Adkisson et al. (hereinafter “Adkisson”).
Regarding independent claim 1, Masuda (Fig. 13) discloses a semiconductor device, comprising:
a plurality of photodiodes 42 (¶ 0142);
a semiconductor structure 41 (¶¶ 0126, 0054) overlapping the plurality of photodiodes, the semiconductor structure comprising a plurality of microstructures 48 (¶ 0132) on a backside (top of 41) of the semiconductor structure 41;
a dielectric layer 114 (¶ 0130; alternatively, 46, labelled in Fig. 11, ¶ 0061) over the plurality of microstructures of the semiconductor structure;
a color filter layer 51 (¶ 0129) over the dielectric layer 46, wherein a vertical distance from the color filter layer 51 to one of the plurality of microstructures 48 is less than a vertical distance from one of the plurality of photodiodes 42 to said one of the plurality of microstructures (vertical distance from 51 to the top of a tip of 48 is less than the vertical distance from 42 to that tip of 48),
wherein the plurality of microstructures 48 form a zigzag pattern having alternating peaks and valleys (Fig. 13), wherein a vertical distance A (annotated Fig. 13 below) from the valleys to the color filter layer 51 is greater than a vertical distance B (annotated Fig. 13 below) from the peaks to the color filter layer 51 (see annotated figure below); and
a micro-lens 52 (¶ 0129) over the color filter layer 51.
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Masuda fails to expressly disclose vertical distance A is less than a vertical distance from the valleys to the photodiodes. In the same field of endeavor, Adkisson (Fig. 1A) discloses a semiconductor device including a plurality of microstructures 101 (¶ 0089), and teaches modifying the height h (Fig. 1A) of the microstructures 101 to increase light transmission (¶ 0092). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the height of the microstructures of Masuda, yielding the recited vertical distance relationship above, for the purpose of optimizing light transmission and improving device performance.
Regarding claim 4, Masuda and Adkisson disclose the semiconductor device of claim 1, Masuda (Fig. 13) further discloses wherein the dielectric layer 46 forms an interface with the plurality of microstructures 48, and the interface has a zigzag pattern in a cross-sectional view (Fig. 13).
Regarding claim 5, Masuda and Adkisson disclose the semiconductor device of claim 1, wherein the plurality of microstructures 48 are formed of silicon (¶ 0054).
Regarding claim 6, Masuda and Adkisson disclose the semiconductor device of claim 1, Masuda (Fig. 13) further discloses wherein a thickness of the dielectric layer 114 is less than a thickness of the color filter layer 51 (Fig. 13).
Regarding claim 7, Masuda and Adkisson disclose the semiconductor device of claim 1, Masuda (Fig. 13) further discloses wherein each of the plurality of microstructures 48 has a pointed top from a cross-sectional view (Fig. 13).
Regarding claim 8, Masuda and Adkisson disclose the semiconductor device of claim 1, Masuda (Fig. 13) further discloses wherein the microstructures 48 continuously extend from the backside (top) of the semiconductor structure 41 (Fig. 13).
Regarding independent claim 16, Masuda (Fig. 15) discloses a semiconductor device, comprising:
a plurality of photo-sensing pixel regions 42 (¶¶ 0151, 0142);
a semiconductor region 41 (¶¶ 0126, 0054) covering the plurality of photo-sensing pixel regions, the semiconductor region comprising a plurality of microstructures 48 (¶ 0132) on a backside (top of 41) of the semiconductor region 41; and
a dielectric layer 112 (¶ 0130; alternatively 46, labelled in Fig. 11, ¶ 0061) over the plurality of microstructures 48 of the semiconductor region, wherein a thickness of the dielectric layer 112 is less than a vertical distance from the plurality of photo-sensing pixel regions 42 to the plurality of microstructures 48 (Fig. 15; alternatively, thickness of 46 as measured from a top tip of 48 to the top of 46 is less than a vertical distance from 42 to said top tip of 48), wherein a bottommost position of the dielectric layer 112 (or 46) is higher than a topmost position of the plurality of photo-sensing pixel regions 42 (Fig. 15); and
a color filter layer 51 (¶ 0129) over the dielectric layer.
Masuda fails to expressly disclose: wherein a vertical distance from the bottommost position of the dielectric layer to the topmost positions of the plurality of photo-sensing pixel regions is greater than a vertical distance from the bottommost position of the dielectric layer to the color filter. In the same field of endeavor, Adkisson (Fig. 1A) discloses a semiconductor device including a plurality of microstructures 101 (¶ 0089), and teaches modifying the height h (Fig. 1A) of the microstructures 101 to increase light transmission (¶ 0092). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the height of the microstructures of Masuda, thus affecting the dimensions of the dielectric layer 112 (or 46) and yielding the recited vertical distance relationship above, for the purpose of optimizing light transmission and improving device performance.
Regarding claim 17, Masuda and Adkisson disclose the semiconductor device of claim 16, Masuda (Fig. 15) discloses wherein the dielectric layer 46 has a zigzag surface (Fig. 15).
Regarding claim 18, Masuda and Adkisson disclose the semiconductor device of claim 17, Masuda (Fig. 15) discloses wherein the zigzag surface of the dielectric layer 46 (labelled in Fig. 11) is in contact with the plurality of microstructures 48 (Fig. 15).
Regarding claim 19, Masuda and Adkisson disclose the semiconductor device of claim 17, Masuda (Fig. 15) discloses wherein the dielectric layer 46 (labelled in Fig. 11) has a top surface (interfacing with 51) opposite the zigzag surface (bottom), and the top surface is more planar than the zigzag surface (Fig. 15).
Regarding independent claim 21, Masuda (Fig. 15) discloses a semiconductor device, comprising: a plurality of photo-sensing regions 42 (¶¶ 0151, 0142);
a semiconductor structure 41 (¶¶ 0126,0054) over the plurality of photo-sensing regions, the semiconductor structure comprising a plurality of microstructures 48 (¶ 0132) on a backside (top of 41) of the semiconductor structure 41;
a dielectric layer 114 (¶ 0130; alternatively 46, labelled in Fig. 11, ¶ 0061) over the plurality of microstructures 48 of the semiconductor structure, wherein a thickness of the dielectric layer 114 is less than a vertical distance from one of the plurality of photo-sensing regions 42 to one of the plurality of microstructures 48 (Fig. 15; alternatively, thickness of 46 as measured from a top tip of 48 to the top of 46 is less than a vertical distance from 42 to said top tip of 48),
wherein an entirety of the dielectric layer 114 (or 46) is above top surfaces of the plurality of photo-sensing regions 42 (Fig. 15);
a color filter layer 51 (¶ 0129) over the dielectric layer; and
a micro-lens 52 (¶ 0129) over the color filter layer 51.
Masuda fails to expressly disclose: wherein a vertical distance from a bottommost position of the dielectric layer to a topmost positions of the plurality of photo-sensing pixel regions is greater than a vertical distance from the bottommost position of the dielectric layer to the color filter. In the same field of endeavor, Adkisson (Fig. 1A) discloses a semiconductor device including a plurality of microstructures 101 (¶ 0089), and teaches modifying the height h (Fig. 1A) of the microstructures 101 to increase light transmission (¶ 0092). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the height of the microstructures of Masuda, thus affecting the dimensions of the dielectric layer 112 (or 46) and yielding the recited vertical distance relationship above, for the purpose of optimizing light transmission and improving device performance.
Regarding claim 22, Masuda and Adkisson disclose the semiconductor device of claim 21, Masuda (Fig. 15) further discloses wherein the dielectric layer 114 comprises silicon oxide, silicon nitride or silicon oxynitride (¶ 0130).
Regarding claim 23, Masuda and Adkisson disclose the semiconductor device of claim 21, Masuda (Fig. 15) further discloses wherein the dielectric layer 46 forms an interface with the plurality of microstructures 48 of the semiconductor structure, and an entirety of the interface is a zigzag pattern in a cross-sectional view (Fig. 15).
Regarding claim 24, Masuda and Adkisson disclose the semiconductor device of claim 21, Masuda (Fig. 15) further discloses wherein the plurality of microstructures 48 are formed of an epitaxial material. The limitation “formed of an epitaxial material” is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966. Here, Masuda discloses the plurality of microstructures 48 are formed of silicon (¶ 0054), a material that is known in the art to be capable of being formed by epitaxy.
Regarding claim 25, Masuda discloses the semiconductor device of claim 21, Masuda (Fig. 15) further discloses wherein the plurality of microstructures 48 are formed of silicon (¶ 0054).
Regarding claim 26, Masuda and Adkisson disclose the semiconductor device of claim 21, Masuda (Fig. 15) further discloses wherein the color filter layer 51 is in contact with the dielectric layer 46 (labelled in Fig. 11).
Regarding claim 27, Masuda and Adkisson disclose the semiconductor device of claim 21, Masuda (Fig. 15) further discloses wherein the micro-lens 52 have a width greater than a width of one of the plurality of microstructures 48 (Fig. 15).
Regarding claim 28, Masuda and Adkisson disclose the semiconductor device of claim 1, however fail to expressly disclose: wherein the zigzag pattern continuously extends across the plurality of photodiodes and across a region between the plurality of photodiodes. In the same field of endeavor, Adkisson (Fig. 28A) discloses a semiconductor device including microstructures 282 (¶ 0158) that continuously extend across a plurality of photodiodes 8 (¶ 0163) and across a region between the plurality of photodiodes (Fig. 28A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Masuda and Adkisson to provide the zigzag pattern continuously extending across the plurality of photodiodes and across a region between the plurality of photodiodes, as taught by Adkisson, for the purpose of providing an art-recognized alternative configuration of microstructures for the purpose of enhancing light transmission (Adkisson, ¶ 0161).
Regarding claim 29, Masuda and Adkisson disclose the semiconductor device of claim 16, however fail to expressly disclose: wherein the plurality of microstructures form a zigzag pattern continuously extending across the plurality of photo-sensing pixel regions and across a region between the plurality of photo-sensing pixel regions. In the same field of endeavor, Adkisson (Fig. 28A) discloses a semiconductor device including microstructures 282 (¶ 0158) that continuously extend across a plurality of photodiodes 8 (¶ 0163) and across a region between the plurality of photodiodes (Fig. 28A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Masuda and Adkisson to provide the zigzag pattern continuously extending across the plurality of photodiodes and across a region between the plurality of photodiodes, as taught by Adkisson, for the purpose of providing an art-recognized alternative configuration of microstructures for the purpose of enhancing light transmission (Adkisson, ¶ 0161).
Regarding claim 30, Masuda and Adkisson disclose the semiconductor device of claim 21, wherein the plurality of microstructures 48 form a zigzag pattern (Masuda, Fig. 15), however fail to expressly disclose: vertically overlapping a region between the plurality of photo-sensing regions. In the same field of endeavor, Adkisson (Fig. 28A) discloses a semiconductor device including microstructures 282 (¶ 0158) that vertically overlap a region between a plurality of photodiodes 8 (¶ 0163; Fig. 28A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Masuda and Adkisson to provide the zigzag pattern vertically overlapping a region between the plurality of photodiodes, as taught by Adkisson, for the purpose of providing an art-recognized alternative configuration of microstructures for the purpose of enhancing light transmission (Adkisson, ¶ 0161).
Conclusion
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CANDICE Y. CHAN
Examiner
Art Unit 2813
15 June 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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