DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Junghwan Jang et al. (US 20220399315 A1) hereinafter referred to as “Jang”, and further in view of Chen-Hua Yu et al. (US 11244924 B2) hereinafter referred to as “Yu”.
Regarding Claim 1 Jang teaches
A method of making a semiconductor device (Fig 2h-2s), comprising:
providing an e-bar (138, and 140a with 118), wherein the e-bar is pre-formed (at least a portion of the e-bar is preformed Para [0022] Fig 2h) with a plurality of vertical interconnects (118) physically connected to each other (through 140a) as part of the e-bar;
depositing an encapsulant (fig 2j element148) over the e-bar;
backgrinding a first surface of the encapsulant to expose the e-bar (Fig 2k, Para [0024]);
forming a first interconnect structure (Fig 2n, element162) over the first surface of the encapsulant; and
forming a second interconnect structure (Fig 2r, element 170) over a second surface of the encapsulant opposite the first surface (Fig 2r) ,
wherein the second interconnect structure (170) is electrically coupled to the first interconnect structure (162) through the vertical interconnects (118) of the e-bar. (Fig 2r Para [0025][0029])
Jang only teaches the single layered interconnect structure and does not teach
a first build-up interconnect structure.
a second build-up interconnect structure
Yu teaches a package configuration where near the e-bars and the encapsulant layers is a
a first build-up interconnect structure.
a second build-up interconnect structure. (Fig 4, elements 48 and 46)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Jang such that both of the interconnect structures are a build-up interconnect structure, as described in Yu because both the single layer and multilayer structures are known interconnect structures that complete the same goal of electrical connection between layers the modification is thus a simple substitution of known elements for a predictable result. (Yu Col.5 lines 14-22, Jang Para [0025], [0029])
Regarding Claim 2 Jang in view of Yu teaches
The method of claim 1,
Jang further teaches
further including providing the e-bar to include a base (Fig 2p, at least a portion of element 122) and a plurality of conductive pillars (138 and 118) extending from (built vertically above) the base.
Regarding Claim 3 Jang in view of Yu teaches
The method of claim 2,
Jang further teaches
further including backgrinding the second surface of the encapsulant to remove the base (Para [0028]).
Regarding Claim 4 Jang in view of Yu teaches
The method of claim 1,
Jang further teaches
wherein the e-bar includes a core (148) and a conductive via (138) extending through the core.
Regarding Claim 5 Jang in view of Yu teaches
The method of claim 1,
Jang further teaches
wherein the e-bar includes a passive electrical component. (Fig 2i element 140a, Para [0013], [0022])
Regarding Claim 6 Jang in view of Yu teaches
The method of claim 1,
Jang in view of Yu further teaches
further including mounting a semiconductor die (Jang Fig 2n element 166a and/or 166b) on the first build-up interconnect structure or second build-up interconnect structure
Regarding Claim 7 Jang teaches
A method of making a semiconductor device (Fig 2h-2s), comprising:
providing an e-bar (138 with 126a-126f with 148, and 140a with 118) including an insulating core (148 Para [0023]) and a conductive via (138 and 126a-126f) extending completely through the insulating core;
disposing the e-bar over a carrier (122), wherein the e-bar is pre-formed (the portion 140a and 118 are preformed) prior to disposing the e-bar over the carrier;
depositing an encapsulant (fig 2j element148) over the e-bar and carrier;
backgrinding (Fig 2k, Para [0024]) the encapsulant to expose the e-bar;
forming a interconnect structure (Fig 2n, element 162) over the encapsulant and e-bar; and
removing the carrier (Fig 2q) after forming the interconnect structure.
Jang only teaches the single layered interconnect structure and does not teach
a build-up interconnect structure.
Yu teaches a package configuration where near the e-bars and the encapsulant layers is
a build-up interconnect structure. (Fig 4, elements 48 and 46)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Jang such that the interconnect structure is a build-up interconnect structure, as described in Yu because both the single layer and multilayer structures are known interconnect structures that complete the same goal of electrical connection between layers the modification is thus a simple substitution of known elements for a predictable result. (Yu Col.5 lines 14-22, Jang Para [0025], [0029])
Regarding Claim 11 Jang in view of Yu teaches
The method of claim 7,
Jang further teaches
wherein the e-bar includes a passive electrical component. (Fig 2i element 140a, Para [0013], [0022])
Regarding Claim 12 Jang in view of Yu teaches
The method of claim 7,
Jang in view of Yu further teaches
further including mounting a semiconductor die (Jang Fig 2n element 166a and/or 166b) on the build-up interconnect structure.
Regarding Claim 13 Jang in view of Yu teaches
The method of claim 12, further including:
Jang in view of Yu further teaches
depositing an underfill or second encapsulant (Jang Fig 2p element 168) between the semiconductor die (Jang 166a or 166b) and build-up interconnect structure; and
singulating (Jang Fig 2s) the underfill or second encapsulant, build-up interconnect structure, and encapsulant to form a semiconductor package.(Jang Fig 3)
Regarding Claim 14 Jang teaches
A method of making a semiconductor device (Fig 2h-2s), comprising:
providing an e-bar (138 with 126a-126f with 148, and 140a with 118) including an insulating core (148 Para [0023]) and a conductive via (138 and 126a-126f) extending completely through the insulating core;
depositing an encapsulant (fig 2j element 148) over the e-bar; and
forming a interconnect structure (Fig 2n, element 162 or Fig 2r, element 170) over the encapsulant and e-bar.
Jang only teaches the single layered interconnect structure and does not teach
a build-up interconnect structure.
Yu teaches a package configuration where near the e-bars and the encapsulant layers is a
a build-up interconnect structure. (Fig 4, elements 48 and 46)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Jang such that the interconnect structure is a build-up interconnect structure, as described in Yu because both the single layer and multilayer structures are known interconnect structures that complete the same goal of electrical connection between layers the modification is thus a simple substitution of known elements for a predictable result. (Yu Col.5 lines 14-22, Jang Para [0025], [0029])
Regarding Claim 18 Jang in view of Yu teaches
The method of claim 14,
Jang further teaches
wherein the e-bar includes a passive electrical component. (Fig 2i element 140a, Para [0013], [0022])
Regarding Claim 19 Jang in view of Yu teaches
The method of claim 14,
Jang in view of Yu further teaches
further including mounting a semiconductor die (Jang Fig 2n element 166a and/or 166b) on the build-up interconnect structure.
Regarding Claim 20 Jang in view of Yu teaches
A semiconductor device (Fig 2h-2s), comprising:
an e-bar (138 with 126a-126f with 148, and 140a with 118) including an insulating core (148 Para [0023]) and a conductive via (138 and 126a-126f) extending completely through the insulating core;
an encapsulant deposited (fig 2j element148) over the e-bar; and
a interconnect structure (Fig 2n, element 162 or Fig 2r, element 170) formed over the encapsulant and e-bar.
Jang only teaches the single layered interconnect structure and does not teach
a build-up interconnect structure.
Yu teaches a package configuration where near the e-bars and the encapsulant layers is a
a build-up interconnect structure. (Fig 4, elements 48 and 46)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Jang such that the interconnect structure is a build-up interconnect structure, as described in Yu because both the single layer and multilayer structures are known interconnect structures that complete the same goal of electrical connection between layers the modification is thus a simple substitution of known elements for a predictable result. (Yu Col.5 lines 14-22, Jang Para [0025], [0029])
Regarding Claim 23 Jang in view of Yu teaches
The semiconductor device of claim 20,
Jang further teaches
wherein the e-bar includes a passive electrical component.(Fig 2i element 140a, Para [0013], [0022])
Regarding Claim 24 Jang in view of Yu teaches
The semiconductor device of claim 20,
Jang in view of Yu further teaches
further including a semiconductor die (Jang Fig 2n element 166a and/or 166b) mounted on the build-up interconnect structure.
Regarding Claim 25 Jang in view of Yu teaches
The semiconductor device of claim 24,
Jang in view of Yu further teaches
further including an underfill (Jang Fig 2p element 168) disposed between the semiconductor die (Jang 166a or 166b) and build-up interconnect structure
Response to Arguments
Applicant's arguments filed 06-24-2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies i.e.,
the e-bar is pre-formed with a plurality of vertical interconnects physically connected to each other as part of the e-bar
an e-bar including an insulating core and a conductive via extending completely through the insulating core
are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Argument are also found unpersuasive since examiner disagrees and believes the limitations “the e-bar is pre-formed with a plurality of vertical interconnects physically connected to each other as part of the e-bar” and “an e-bar including an insulating core and a conductive via extending completely through the insulating core” are taught in the previously presented references. See rejection above for a more detailed description.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu; Kai (US 20170033062 A1), Chan; Kai Chong (US 20250226334 A1), LIN; YAOJIAN (US 20230187422 A1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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