DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1- 4 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al. (US 20190238134) herein referred to as Lee Fig. 42G
As to claim 1, Lee teaches a chip package structure, comprising:
a metal wiring layer (interposer 551, Fig 42G, Lee), wherein the metal wiring layer is provided with a first surface and a second surface (Annotated 1st and 2nd surface Fig 42G, Lee) ;
a plurality of first chips (1st IC chip 317, Fig. 42 G, Lee), wherein a front surface of each of the plurality of first chips is flip-chipped on the first surface of the metal wiring layer (interposer 551, Fig 42G, Lee);
a first molding layer ([1117] polymer layer 318, such as resin, is formed by molding to cover the memory IC chips 317), wherein the first molding layer covers the plurality of first chips (317, Lee), and
a side of the first molding layer (318) far away from the metal wiring layer is flush with a back surface of each of the plurality of first chips (317, FIG. 31D [0108]“Applying a CMP, polishing or grinding process to planarize the surface of the applied material, resin or compound to a level where the top surfaces of all backsides of the IC chips and top surfaces of TPVs are fully exposed”);
a second chip (2nd, semiconductor chip 100, Fig. 42 G, Lee), wherein a front surface of the second chip is flip-chipped on the second surface of the metal wiring layer (interposer 551, Fig 42G, Lee);
a first metal pillar (1st metal pillar 582, [0967] Fig 42G, Lee), wherein the first metal pillar is formed on the second surface of the metal wiring layer (interposer 551, Fig 42G, Lee);
a second molding layer (565), wherein the second molding layer covers the second chip (100) and the first metal pillar, ([0928] “a polymer layer 565, e.g., resin or compound, may be applied to fill the gaps between the semiconductor chips 100 and cover the backsides 100a of the semiconductor chips 100”) and
a side of the second molding layer (565) far away from the metal wiring layer (551) is flush with a back surface of the second chip (100) and an end surface of the first metal pillar (565); and
a second metal pillar ([1007] interconnection metal layers 77, Lee), wherein the second metal pillar is formed on the side of the second molding layer (565) far away from the metal wiring layer (551), and
the second metal pillar (77) is at least partially connected to the corresponding first metal pillar (582).
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As to claim 2, Lee teaches the chip package structure according to claim 1, as discussed above, and further discloses wherein
a filler (Fig. 42G 628[0092] an underfill 114 may be filled into a ga) is provided between the front surface of each of the plurality of first chips (317) and the metal wiring layer (551).
As to claim 3, Lee teaches the chip package structure according to claim 1, as discussed above, and further discloses wherein
a filler (114) is provided between the front surface of the second chip (100) and the metal wiring layer (551).
As to claims 4 , Lee teaches the chip package structure according to claim 1, as discussed above, and further comprising:
an insulation layer ([1010 the BISD 79 may comprise 1 to 6 layers), wherein the insulation layer is positioned on the side of the second molding layer (565) away from the metal wiring layer (551), and
the second metal pillar (77) penetrates through the insulation layer (Fig. 42G, layer 79).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190238134) herein referred to as Lee.
As to claim 6, Lee teaches a preparation method for a chip package structure, comprising the following steps:
S1: preparing a carrier board, and preparing a separation layer on an upper surface of the carrier board ([0083] carrier board is used as temporary layer for transfer as shown in Fig. 29N) ;
S2: preparing a metal wiring layer on a surface of the separation layer [0922-0927];
S3: flip-chipping front surfaces of a plurality of first chips on a surface of the metal wiring layer [0062];
S4: molding the plurality of first chips to form a first package body [1113], wherein the first package body comprises the plurality of first chips and a first molding layer covering the plurality of first chips [1117];
S5: thinning a surface of the first package body far away from the metal wiring layer, and thinning the first molding layer or simultaneously thinning the first molding layer and the plurality of first chips [0073];
S8: flip-chipping a front surface of a second chip on the surface of the metal wiring layer [0072];
S9: molding [0928] the second chip and the first metal pillar to form a second package body, wherein the second package body comprises the second chip [31D], the first metal pillar and a second molding layer covering the second chip and the metal pillar [0989];
S10: thinning a surface of the second package body far away from the metal wiring layer, thinning the second chip, the first metal pillar and the second molding layer, and exposing the first metal pillar and the second chip [0073]; and
S11: processing a surface that is of the second package body far away from the metal wiring layer to obtain a second metal pillar, and processing a solder ball [1104] on an end surface of the second metal pillar, wherein the second metal pillar is at least partially connected to the corresponding first metal pillar [1007-1010].
S7: processing a first metal pillar connected to the metal wiring layer on the metal wiring layer ([0960] “through package vias (TPVs) 582 may be formed on the front side of the interposer 551”);
Lee does not appear to expressly disclose:
the step S6: “removing the carrier board by removing the separation layer”;
the step S7: “turning over a combination of the first package body and the metal wiring layer to enable the metal wiring layer to be arranged upwards”, and
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to utilize a flip chip process involving the step of removing the carrier board by removing the separation layer. Carrier removal in flip chip mounting is the controlled separation of a fragile device wafer from a rigid support carrier once the flip chip die has been mounted and processed. Therefore, though not explicitly taught, the Lee method disclosed in [0062], obviously includes the process of S6, so as to use an industrially tested and accepted method of manufacturing.
Also, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to utilize a flip chip process, involving turning over a combination of the first package body and the metal wiring layer to enable the metal wiring layer to be arranged upwards. In flip chip mounting, the "flipping" process is the critical step where a semiconductor die is turned completely upside down so its active circuitry (and conductive bumps) face downwards to mount directly onto the packaging substrate or circuit board. Therefore, though not explicitly taught, the Lee method disclosed in [0062] obviously includes the process of S7, so as to use an industrially tested and accepted method of manufacturing.
As to claim 7, Lee teaches the preparation method for the chip package structure according to claim 6, as discussed above wherein
Lee does not appear to expressly disclose "
the step S4, “before molding the plurality of first chips, further comprises providing a filler between the front surface of each of the plurality of first chips and the metal wiring layer.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to provide a filler inside the mold before it is applied. Adding the filler components first, (obvious) serves several critical engineering purposes during the encapsulation process.
Therefore, though not explicitly taught, the Lee method disclosed in [0985-0992] includes applying a filler before the molding encapsulant is laced on top of the filler, so as to use an industrially tested and accepted method of manufacturing a protective layer.
As to claim 8, Lee teaches the preparation method for the chip package structure according to claim 6, as discussed above wherein
Lee does not appear to expressly disclose:
the step S9, “before molding the second chip and the first metal pillar, further comprises providing a filler between the front surface of the second chip and the metal wiring layer”.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to provide a filler inside the mold before it is applied. Adding the filler component first, (obvious) serves several critical engineering purposes during the encapsulation process.
Therefore, though not explicitly taught, the Lee method disclosed in [0985-0992] includes applying a filler before the molding encapsulant is placed on top of the filler, so as to use an industrially tested and accepted method of manufacturing a protective layer.
As to claim 9, Lee teaches the preparation method for the chip package structure according to claim 6, as discussed above wherein
the step S11 further comprises processing an insulation layer ([1010 the BISD 79 may comprise 1 to 6 layers) on the surface the second package body far away from the metal wiring layer, wherein the second metal pillar (77) penetrates (See Fig. 42G) through the insulation layer.
Claim(s) 5 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190238134) herein referred to as Lee, in view of Blum et al. (US 5493003) herein referred to as Blum.
As to claims 5, Lee teaches the chip package structure according to claim 4,
Lee does not appear to expressly disclose: “the insulation layer comprises a PI film.”
Using a polyimide insulating film in IC manufacturing especially in processes like wafer-level packaging and redistribution layers (RDL)—provides essential high-temperature resilience, stress relief, and excellent dielectric properties. The Lee reference does not teach a PI material is used for the insulation layer (79).
Blum teaches polyimide coatings are used as insulation layers in the structures of microchips or as buffer layers between the finished chip and the chip housing. Polyimide layers are widely used as insulation layers in semiconductor manufacturing due to their physical characteristics as high-performance polymer material used for insulation, protection, and stress relief .
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the insulation layer (79) of a PI film, due to its high thermal stability, so as to use an industrially tested and accepted method of manufacturing.
As to claim 10, the combined Lee/Blum device teaches the preparation method for the chip package structure according to claim 9, wherein
the insulation layer comprises a PI film (See rejection of claim 5)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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