DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al, US 20230066598 A1 in view of Hsu et al, US 20230317671 A1.
PNG
media_image1.png
519
810
media_image1.png
Greyscale
PNG
media_image2.png
512
564
media_image2.png
Greyscale
Pertaining to claim1, Lai tec teaches ( see figs.1G and 1F-1 above for example ) A forming method for a semiconductor package structure[146], comprising: providing an encapsulant [120], wherein the encapsulant comprises a first surface and a second surface that are opposite and peripheral side surfaces [140] that are positioned between the first surface and the second surface, the first surface is provided with protruding connection terminals[134,136 ], and junction between the first surface and the peripheral side surfaces are provided with four top corners[120C1 and 120C4]; providing a substrate[160], wherein the substrate[160] comprises a flip-chip area, and the flip- chip area is provided with four corner areas[170] corresponding to four top corners [120C1 and 120C4] of the encapsulant[146]; correspondingly forming four trenches[182] in the substrate[160] in the four corner areas[170] and/or or around the four corner areas or in the four corner areas and around the four corner areas at the same time;
flip-chipping the encapsulant [146] on the flip-chip area of the substrate[160] ( see fig.1G above), so that the protruding connection terminals on the first surface of the encapsulant are electrically connected to the substrate[160]; filling the four trenches and spaces between the four trenches and the first surface of the encapsulant with a high-modulus first underfill layer[180]; and filling a remaining space between the encapsulant[146] and the substrate[160] with a low-modulus second underfill layer[138],
Lai is silent wherein the wherein the low modulus second underfill layer[138], is less than the high modulus first underfill layer[180],
However, in the same field of endeavor, Hsu teaches ( see fig5B for example) silent wherein the wherein the first modulus[950] is less than the high modulus[910M] ( see para 0058). In view of Hsu, it would have been obvious to one of ordinary skill in the art to have the High modulus underfill surrounding the low modulus underfill as a result, the tensile stress concentrated at the corner of the semiconductor die 120 of Lai may be reduced or mitigated ( see para 0153 of Lai).
Pertaining to claim 2, Lai in view of Hsu teaches the forming method for the semiconductor package structure according to claim 1, wherein the Hsu teaches the high-modulus first underfill layer [910M] has a storage modulus greater than or equal to 10 Gpa, and the low-modulus second underfill layer[950] has a storage modulus less than or equal to 9 Gpa ( see para 0058).
Pertaining to claim3, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The forming method for the semiconductor package structure according to claim 1, wherein the high-modulus first underfill layer is made of a thermosetting resin ( see para 0060,0103).
Pertaining to claim 4, Lai in view of Hsu teaches the forming method for the semiconductor package structure according to claim 1, wherein the Hsu teaches wherein the high-modulus first underfill layer is formed by a dispensing process, and the low-modulus second underfill layer is formed by an underfill process ( see abstract or 0002 and 0053).
Pertaining to claim5, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The forming method for the semiconductor package structure according to claim 1, wherein the four trenches[170] are correspondingly positioned in the substrate[160] in the four corner areas[120C1 and 120C4, or the four trenches are correspondingly positioned in the substrate around the four corner areas, or the four trenches are positioned in the substrate both in the four corner areas and around the four corner areas.
Pertaining to claim 6, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The forming method for the semiconductor package structure according to claim 1, wherein the substrate [160] comprises a solder mask layer[168], and the four trenches[170] are positioned in the solder mask layer[168].
Pertaining to claim7, Lai tec teaches ( see figs.2 for example ) The forming method for the semiconductor package structure according to claim 5, wherein each of the four trenches[170] is a square trench or an "L" shaped trench.
Pertaining to claim 8, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The forming method for the semiconductor package structure according to claim 1, wherein the encapsulant[146] is a 2.5D encapsulant ( Fig 1G).
Pertaining to claim 9, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The forming method for the semiconductor package structure according to claim 8, wherein the 2.5D encapsulant [146]comprises an interposer [106] and a plurality of semiconductor chips[120] flip-chipped on the interposer[106], an upper surface and a lower surface of the interposer are provided with a plurality of pads, the interposer is provided with connection layers that are electrically connected to at least part of the plurality of pads on the upper surface and the lower surface, the plurality of semiconductor chips[120] are flip-chipped on the upper surface of the interposer, and the protruding connection terminals are connected to the plurality of pads on the lower surface of the interposer.
Pertaining to claim10, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The forming method for the semiconductor package structure according to claim 1, wherein the encapsulant [146] comprises a semiconductor chip[120] and a molding layer[140] for molding the semiconductor chip[120], and the protruding connection terminals are electrically connected to the semiconductor chip[120].
Pertaining to claim11, Lai tec teaches ( see figs.1G and 1F-1 above for example ) A semiconductor package structure, comprising: a encapsulant[146], wherein the encapsulant[146] comprises a first surface and a second surface that are opposite and peripheral side surfaces that are positioned between the first surface and the second surface, the first surface is provided with protruding connection terminals[134,136], and junction between the first surface and the peripheral side surfaces are provided with four top corners [120C1 and 120C4]; a substrate[160], wherein the substrate [160] comprises a flip-chip area, and the flip-chip area is provided with four corner areas [170] corresponding to four top corners [120C1 and 120C4] of the encapsulant [146]; corresponding four trenches[182] positioned in the substrate [160] in the four corner areas [170] or around the four corner areas or in the four corner areas and around the four corner areas at the same time;
wherein the encapsulant [146] is flip-chipped on the flip-chip area of the substrate[160], so that the protruding connection terminals [134,136] on the first surface of the encapsulant [146] are electrically connected to the substrate[160]; first underfill layer[180] filling the four trenches [182] and spaces between the four trenches[182] and the first surface of the encapsulant[146]; and a second underfill layer[138] filling a remaining space between the encapsulant [146] and the substrate[160],
Lai is silent wherein the wherein the low modulus second underfill is less than the high modulus first underfill.
However, in the same field of endeavor, Hsu teaches ( see fig5B for example) silent wherein the wherein the first modulus[950] is less than the high modulus[910M] ( see para 0058). In view of Hsu, it would have been obvious to one of ordinary skill in the art to have the High modulus underfill surrounding the low modulus underfill as a result, the tensile stress concentrated at the corner of the semiconductor die 120 of Lai may be reduced or mitigated ( see para 0153 of Lai).
Pertaining to claim 12, Lai in view of Hsu teaches The semiconductor package structure according to claim 11, wherein the Hsu teaches the high-modulus first underfill layer [910M] has a storage modulus greater than or equal to 10 Gpa, and the low-modulus second underfill layer[950] has a storage modulus less than or equal to 9 Gpa ( see para 0058).
Pertaining to claim 13, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The semiconductor package structure according to claim 11, wherein the high-modulus first underfill layer is made of a thermosetting resin ( see para 0060,0103).
Pertaining to claim 14, Lai The semiconductor package structure according to claim 11, wherein the four trenches [170] are correspondingly positioned in the substrate[160] in the four corner areas [120C1 and 120C4], or the four trenches are correspondingly positioned in the substrate around the four corner areas, or the four trenches are positioned in the substrate both in the four corner areas and around the four corner areas.
Pertaining to claim15, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The semiconductor package structure according to claim 11, wherein the substrate[160] comprises a solder mask layer[168], and the four trenches[170] are positioned in the solder mask layer[170].
Pertaining to claim16, Lai tec teaches ( see figs.2G) the semiconductor package structure according to claim 14, wherein each of the four trenches [170] are a square trench or an "L"-shaped trench.
Pertaining to claim17, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The semiconductor package structure according to claim 14, wherein the encapsulant[146] is a 2.5D encapsulant ( see fig.1G).
Pertaining to claim18, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The semiconductor package structure according to claim 17, wherein the 2.5D encapsulant [146] comprises an interposer[106A], a plurality of semiconductor chips [120] flip-chipped on the interposer[106] and a molding layer [140] for molding the plurality of chips[120], an upper surface and a lower surface of the interposer [106] are provided with a plurality of pads, the interposer [106] is provided with connection layers that are electrically connected to at least part of the plurality of pads on the upper surface and the lower surface, the plurality of semiconductor chips[120] are flip-chipped on the upper surface of the interposer[120], and the protruding connection terminals are connected to the plurality of pads on the lower surface of the interposer[160].
Pertaining to claim19, Lai tec teaches ( see figs.1G and 1F-1 above for example ) The semiconductor package structure according to claim 11, wherein the encapsulant[146] comprises a semiconductor chip [120] and a molding layer [140] for molding the semiconductor chip[120], and the protruding connection terminal is electrically connected to the semiconductor chip[120].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAMADOU L DIALLO whose telephone number is (571)270-5449. The examiner can normally be reached M-F: 9:00AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FERNANDO TOLEDO can be reached at (571)272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
Prosecution Insights