DETAILED ACTION
This Office action responds to the invention filed on 04/26/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ham (US 2022/0210921) in view of Kim (US 2021/0407962).
Regarding claim 1, Ham shows (see, e.g., Ham: figs. 10 and 12) shows most aspects of the instant invention including a semiconductor package, comprising:
A substrate 113 having a first surface and a second surface opposite to the first surface
A first insulating layer 111/112 disposed on the first surface of the substrate 113 and having a first concave portion
A first interposer 200 disposed in the first concave portion of the first insulating layer 111/112
The first interposer comprising a plurality of first wiring patterns 222/223/231/232
A first electronic component 310 overlapping with a first portion of the first interposer 200 and electrically connected with the first wiring patterns 222/223/231/232 of the first interposer 200
A second electronic component 320 overlapping with a second portion of the first interposer 200 and electrically connected with the first wiring patterns 222/223/231/232 of the first interposer 200
However, Ham fails (see, e.g., Ham: figs. 10 and 12) to show that the first interposer 200 comprising a first semiconductor layer. Ham shows (see, e.g., Ham: figs. 10 and 12) that the first interposer 200 comprising an insulating layer 211/212/213 (see, e.g., Ham: par. [0074]).
Kim, in a similar device to Ham, teaches (see, e.g., Kim: fig. 2) that the first interposer 220 comprises a first semiconductor layer 221 (see, e.g., Kim: par. [0041]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the insulating layer of Ham or the semiconductor layer of Kim because these were recognized in the semiconductor art for their use as layers of interposer/bridges in semiconductor device packages, as taught by Ham and Kim, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Ham in view of Kim shows (see, e.g., Kim: fig. 2) that:
The first interposer 220 is a first semiconductor interposer
The plurality of first wiring patterns 222 is formed on the first semiconductor later 221
Regarding claim 2, Ham in view of Kim shows (see, e.g., Ham: figs. 10 and 12) that:
The first insulating layer 111/112 comprises a first insulating sub-layer 111 and a second insulating sub-layer 112 formed on the first insulating sub-layer 111
The first concave portion of the first insulating layer 111/112 comprises a first window formed in the second insulating sub-layer 112
Regarding claim 10, Ham shows (see, e.g., Ham: figs. 4-12) shows most aspects of the instant invention including a method for making a semiconductor package, comprising:
Providing a substrate 113, the substrate 113 having a first surface and a second surface opposite to the first surface
Forming a first insulating layer 111/112 on the first surface of the substrate 113, the first insulating layer 111/112 having a first concave portion formed therein
Embedding a first interposer 200 into the first concave portion of the first insulating layer 111/112
The first interposer 200 comprising a plurality of first wiring patterns 222/223/231/232
Mounting a first electronic component 310 on the first interposer 200
The first electronic component 310 overlapping with a first portion of the first interposer 200 and being electrically connected with the first wiring patterns 222/223/231/232 of the first interposer 200
Mounting a second electronic component 320 on the first interposer 200
The second electronic component 320 overlapping with a second portion of the first interposer 200 and being electrically connected with the first wiring patterns 222/223/231/232 of the first interposer 200
However, Ham fails (see, e.g., Ham: figs. 10 and 12) to show that the first interposer 200 comprising a first semiconductor layer. Ham shows (see, e.g., Ham: figs. 10 and 12) that the first interposer 200 comprising an insulating layer 211/212/213 (see, e.g., Ham: par. [0074]).
Kim, in a similar device to Ham, teaches (see, e.g., Kim: fig. 2) that the first interposer 220 comprises a first semiconductor layer 221 (see, e.g., Kim: par. [0041]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the insulating layer of Ham or the semiconductor layer of Kim because these were recognized in the semiconductor art for their use as layers of interposer/bridges in method for making semiconductor device packages, as taught by Ham and Kim, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Ham in view of Kim shows (see, e.g., Kim: fig. 2) that:
The first interposer 220 is a first semiconductor interposer
The plurality of first wiring patterns 222 is formed on the first semiconductor later 221
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ham in view of Kim in further view of Leobandung (US 2019/0164806).
Regarding claim 3, Ham in view of Kim shows (see, e.g., Ham: figs. 10 and 12) that the first semiconductor interposer 200 and the first insulating layer 111/112.
However, Ham in view of Kim fails (see, e.g., Ham: figs. 10 and 12) to show a first adhesive disposed between the first interposer 200 and the first insulating layer 111/112. Leobandung, in a similar device to Ham in view of Kim, shows (see, e.g., Leobandung: figs. 3 and 7A) an adhesive 502 disposed between the first interposer 302 and the first insulating layer 202 (see, e.g., Leobandung: par. [0046]). Also, Leobandung shows (see, e.g., Leobandung: figs. 3 and 7A) that the adhesive material 502 will physically join the silicon bridge chip 300 to the substrate structure 200, providing additional structural support to the assembly (see, e.g., Leobandung: par. [0046]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to have an adhesive, suggested by Leobandung, disposed between the first semiconductor interposer and the first insulating layer in the semiconductor device of Ham in view of Kim to physically join the silicon bridge chip to the substrate structure, and providing additional structural support to the assembly.
Regarding claim 12, Ham in view of Kim shows (see, e.g., Ham: figs. 10 and 12) embedding the first semiconductor interposer 200 into the first concave portion of the first insulating layer 111/112.
However, Ham in view of Kim fails (see, e.g., Ham: figs. 10 and 12) to show the method step of forming a first adhesive on a lower surface of the first concave portion of the first insulating layer 111/112. Leobandung, in a similar method to Ham in view of Kim, shows (see, e.g., Leobandung: figs. 3 and 7A) a method step of forming the first adhesive 502 on a lower surface of the first concave portion of the first insulating layer 202 (see, e.g., Leobandung: par. [0046]). Also, Leobandung shows (see, e.g., Leobandung: figs. 3 and 7A) that the adhesive material 502 will physically join the silicon bridge chip 300 to the substrate structure 200, providing additional structural support to the assembly (see, e.g., Leobandung: par. [0046]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a method step of forming the adhesive, suggested by Leobandung, on a lower surface of the first concave portion of the first insulating layer in the method of Ham in view of Kim to physically join the silicon bridge chip to the substrate structure, and providing additional structural support to the assembly.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ham in view of Kim in further view of Yu (US 2020/0020643).
Regarding claim 4, Ham in view of Kim shows (see, e.g., Ham: figs. 10 and 12) a first insulating layer 111/112, the first electronic component 310, and the second electronic component 320.
However, Ham in view of Kim fails (see, e.g., Ham: figs. 10 and 12) to show a first encapsulant disposed on the first insulating layer 111/112 and encapsulating the first electronic component 310 and the second electronic component 320. Yu, in a similar device to Ham in view of Kim, shows (see, e.g., Yu: fig. 2) a first encapsulant 120 disposed on the first insulating layer 122A/138 and encapsulating the first electronic component 112 and the second electronic component 112 (see, e.g., Yu: par. [0017]). Also, Yu shows (see, e.g., Yu: fig. 2) that the first encapsulant 120 is a molding layer that protects the redistribution layer structure 122, protects the electronic components 112, and defines the space that is incorporated by an electromagnetic interference shielding layer EMI1 (see, e.g., Yu: par. [0017] – [0018]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the first encapsulant, suggested by Yu, disposed on the first insulating layer and encapsulating the first and second electronic components in the semiconductor device of Ham in view of Kim to protect the redistribution layer structure, protect the electronic components, and defines the space that is incorporated by an electromagnetic interference shielding layer.
Regarding claim 13, Ham in view of Kim shows (see, e.g., Ham: figs. 10 and 12) a first insulating layer 111/112, the first electronic component 310, and the second electronic component 320.
However, Ham in view of Kim fails (see, e.g., Ham: figs. 10 and 12) to show a method step of forming a first encapsulant disposed on the first insulating layer 111/112 to encapsulate the first electronic component 310 and the second electronic component 320. Yu, in a similar method to Ham in view of Kim, shows (see, e.g., Yu: fig. 2) a method step of forming a first encapsulant 120 disposed on the first insulating layer 122A/138 to encapsulate the first electronic component 112 and the second electronic component 112 (see, e.g., Yu: par. [0017]). Also, Yu shows (see, e.g., Yu: fig. 2) that the first encapsulant 120 is a molding layer that protects the redistribution layer structure 122, protects the electronic components 112, and defines the space that is incorporated by an electromagnetic interference shielding layer EMI1 (see, e.g., Yu: par. [0017] – [0018]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the methos step of forming the first encapsulant, suggested by Yu, disposed on the first insulating layer and to encapsulate the first and second electronic components in the method of Ham in view of Kim to protect the redistribution layer structure, protect the electronic components, and defines the space that is incorporated by an electromagnetic interference shielding layer.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ham in view of Kim in further view of Lin (US 2013/0337648).
Regarding claim 11, Ham in view of Kim shows (see, e.g., Ham: figs. 10 and 12) that forming the first insulating layer 111/112 on the first surface of the substrate 113 comprises the methos step of forming a first insulating layer 111 on the first surface of the substrate 113.
However, Ham in view of Kim fails (see, e.g., Ham: figs. 10 and 12) to show the method step of forming a first sacrificial pattern on the first insulating sub-layer 111. Lin, in a similar method to Ham in view of Kim, shows (see, e.g., Lin: figs. 1C-1J) a method step of forming a first sacrificial pattern 12 on the first insulating sub-layer 21 (see, e.g., Lin: par. [0058]). Also, Lin shows (see, e.g., Lin: figs. 1C-1J) that the first sacrificial pattern 12 is removed to form a cavity 37 that defines the placement location of the interposer 61 (see, e.g., Lin: par. [0070] and [0077]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the method step of forming the first sacrificial pattern, suggested by Lin, disposed on the first insulating sub-layer in the method of Ham in view of Kim in order to form the first sacrificial pattern that can later be removed to form a cavity that defines the placement location of the interposer.
Allowable Subject Matter
Claim 5-9 and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for objecting the claim 5: The prior art of record neither anticipates nor renders obvious semiconductor package comprising a second insulating layer disposed on the second surface of the substrate and having a second concave portion; a second semiconductor interposer disposed in the second concave portion of the second insulating layer, the second semiconductor interposer comprising a second semiconductor layer and a plurality of second wiring patterns formed on the second semiconductor layer; a third electronic component overlapping with a first portion of the second semiconductor interposer and electrically connected with the second wiring patterns of the second semiconductor interposer; and a fourth electronic component overlapping with a second portion of the second semiconductor interposer and electrically connected with the second wiring patterns of the second semiconductor interposer.
Claims 6-9 are objected because they depend on the on claim 5.
The following is an examiner’s statement of reasons for objecting the claim 14: The prior art of record neither anticipates nor renders obvious a method for making a semiconductor package comprising the substrate having a first surface and a second surface opposite to the first surface; forming a first insulating layer on the first surface of the substrate, the first insulating layer having a first concave portion formed therein; embedding a first semiconductor interposer into the first concave portion of the first insulating layer, the first semiconductor interposer comprising a first semiconductor layer and a plurality of first wiring patterns formed on the first semiconductor layer; mounting a first electronic component on the first semiconductor interposer, the first electronic component overlapping with a first portion of the first semiconductor interposer and being electrically connected with the first wiring patterns of the first semiconductor interposer; and mounting a second electronic component on the first semiconductor interposer, the second electronic component overlapping with a second portion of the first semiconductor interposer and being electrically connected with the first wiring patterns of the first semiconductor interposer.
Claims 15-18 are objected because they depend on the on claim 14.
Conclusion
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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