DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 16-22, 24-27 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Schmitz (US 2006/0049453).
Regarding claim 1, Schmitz discloses a semiconductor device, comprising: a semiconductor layer structure that comprises a drift region (Figs. 2A-2F, numeral 4) having a first conductivity type ([0032]), a well layer (6) having a second conductivity type ([0033]), and a source region (8) having the first conductivity type ([0002]); a first gate trench (26) extending into an upper portion of the semiconductor layer structure (Fig. 2C); a first dielectric layer (18) within the first gate trench (26) and conforming to an interior perimeter of the first gate trench (26); and a first gate electrode (21) within the first gate trench (26) and on the first dielectric layer (18), the first gate electrode (21) having first and second portions that are spaced apart from each other by a second dielectric layer (30) (Fig.2D) .
Regarding claim 2, Schmitz discloses wherein at least a portion of the first dielectric layer (18) on a bottom surface of the first gate trench (26) is free from vertical overlap with the first gate electrode (21) (Fig.2C).
Regarding claim 3, Schmitz discloses wherein the first and second portions (21) are free from contact with each other along an entirety of the first gate trench (26) (Fig.2C).
Regarding claim 4, Schmitz discloses wherein the first gate electrode (21) further comprises a connecting portion (Fig.3b, numeral 42) between and directly connected to the first and second portions of the first gate electrode (21), and wherein the connecting portion is at least partially within the first gate trench (Fig.3B).
Regarding claim 5, Schmitz discloses wherein the connecting portion (42) overlaps vertically with the second dielectric layer (30), and wherein a bottom surface of the connecting portion (42) directly contacts the second dielectric layer (30).
Regarding claim 6, Schmitz discloses wherein the first dielectric layer (18) comprises an oxide ([0034]).
Regarding claim 7, Schmitz discloses wherein the first dielectric layer (Fig.2C, numeral 18) has a substantially uniform thickness along the interior perimeter of the first gate trench (26).
Regarding claim 8, Schmitz wherein the first dielectric layer (18) has a first thickness along a first sidewall of the first gate trench (Fig.4) and has a second thickness (Fig.4, numeral 50) along a bottom surface of the first gate trench that is greater than the first thickness ([0048]).
Regarding claim 16, Schmitz discloses a semiconductor device, comprising: a semiconductor layer structure (Figs. 2A-2F) that comprises a drift region (4) having a first conductivity type ([0032]), a well layer (6) having a second conductivity type ([0033]), and a source region (8) having the first conductivity type ([0033]); a first gate trench (26) extending in the semiconductor layer structure (Fig. 2C); a first dielectric layer (18) within the first gate trench (26)and conforming to an interior perimeter of the first gate trench (26); and a first gate electrode (21) within the first gate trench (26) and on the first dielectric layer (18), the first gate electrode (21) having first and second portions that are spaced apart from each other by a second dielectric layer (30) (Fig. 2D), wherein a maximum width of the second dielectric layer (30)between the first portion and the second portion of the first gate electrode (21) in a transverse direction perpendicular to an extension direction of the first gate trench is equal to a maximum distance between the first portion and the second portion of the first gate electrode (21) in the transverse direction.
Regarding claim 17, Schmitz discloses wherein the first gate electrode (21) further comprises a connecting portion (Fig.3B, numeral 42) between and directly connected to the first and second portions of the first gate electrode (21), and wherein the connecting portions (42) at least partially within the first gate trench (Fig.3B).
Regarding claim 18, Schmitz discloses wherein the connecting portion (42) overlaps vertically with the second dielectric layer, and wherein a bottom surface of the connecting portion (42) directly contacts the second dielectric layer (30).
Regarding claim 19, Schmitz discloses wherein the first dielectric layer (18) comprises an oxide ([0034]).
Regarding claim 20, Schmitz discloses wherein at least a portion of the first dielectric layer (18) on a bottom surface of the first gate trench is free from overlap with the first gate electrode (21) in a vertical direction perpendicular to the transverse direction (Fig.2C).
Regarding claim 21, Schmitz discloses wherein the first dielectric layer (18) has a substantially uniform thickness along the interior perimeter of the first gate trench (26).
Regarding claim 22, Schmitz discloses wherein the first dielectric layer (18) has a first thickness along a first sidewall of the first gate trench and has a second thickness (Fig.4, numeral 50) along a bottom surface of the first gate trench that is greater than the first thickness.
Regarding claim 24, Schmitz discloses a semiconductor device, comprising: a semiconductor layer structure (Figs. 2A-2F) that comprises a drift region (4) having a first conductivity type ([0032]), a well layer (6) having a second conductivity type ([0033]), and a source region (8) having the first conductivity type ([0032]); a first gate trench (26) extending into an upper portion of the semiconductor layer structure (Fig.2C); a first dielectric layer (18) within the first gate trench (26) and conforming to surfaces of the drift region (4), well layer (6), and source region (8) that are exposed by the first gate trench (26) (Fig.2A); and a first gate electrode (21) within the first gate trench and on the first dielectric layer (18), the first gate electrode (21) having first and second portions that are spaced apart from each other by a second dielectric layer (30) (Fig.2D), wherein the first portion and the second portion (21) directly contact the second dielectric layer (30).
Regarding claim 25, Schmitz discloses wherein the first gate electrode (21) further comprises a connecting portion (42) (Fig.3B) between and directly connected to the first and second portions of the first gate electrode (21), and wherein the connecting portion (42) is at least partially within the first gate trench (26).
Regarding claim 26, Schmitz discloses wherein the connecting portion (42) overlaps vertically with the second dielectric layer (18), and wherein a bottom surface of the connecting portion (42) directly contacts the second dielectric layer (30).
Regarding claim 27, Schmitz wherein at least a portion of the first dielectric layer (18) on a bottom surface of the first gate trench is free from overlap with the first gate electrode (21) in a vertical direction perpendicular to an extension direction of the first gate trench (26) (Fig. 2C).
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by CN’795 (CN 106601795, cited in IDS, Machine Translation is provided).
Regarding claim 1, CN’795 discloses a semiconductor device (Figs.3 and 4), comprising: a semiconductor layer structure that comprises a drift region (20) having a first conductivity type, a well layer (30) having a second conductivity type, and a source region (40) having the first conductivity type; a first gate trench (50) extending into an upper portion of the semiconductor layer structure; a first dielectric layer (70) within the first gate trench and conforming to an interior perimeter of the first gate trench; and a first gate electrode (60) within the first gate trench and on the first dielectric layer, the first gate electrode having first and second portions that are spaced apart from each other by a second dielectric layer (80).
Regarding claim 9, CN’795 discloses wherein the semiconductor layer structure further comprises a trench shielding region (Fig.4, numeral 90) having the second conductivity type below the first gate trench (50).
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kim (US 2022/0130998).
Regarding claim 1, Kim discloses a semiconductor device (Fig.6D), comprising: a semiconductor layer structure that comprises a drift region (520) having a first conductivity type, a well layer (532) having a second conductivity type, and a source region (542) having the first conductivity type; a first gate trench (590) extending into an upper portion of the semiconductor layer structure; a first dielectric layer (562) within the first gate trench and conforming to an interior perimeter of the first gate trench (590); and a first gate electrode (564) within the first gate trench and on the first dielectric layer, the first gate electrode having first (564-1) and second portions (564-2) that are spaced apart from each other by a second dielectric layer (566).
Regarding claim 9, Kim discloses wherein the semiconductor layer structure further comprises a trench shielding region (570) having the second conductivity type below the first gate trench (590) (Fig.6D).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891
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