DETAILED ACTION
This Office Action is in response to Application filed April 26, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group I, Species I drawn to the embodiment shown in Figs. 6A-6K and 7A-7K of current application, Subspecies A-1 drawn to the embodiment shown in Fig. 6A of current application, Sub-subspecies a-1 drawn to the embodiment shown in Fig. 9A of current application, and Sub-sub-subspecies I drawn to the embodiment shown in Fig. 18 of current application in the reply filed on June 24, 2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “grain boundaries” recited on line 5 of claim 1 must be shown or the feature canceled from the claim, because (a) as discussed below under 35 USC 112(b) rejections, Applicants do not simply claim “grain boundaries”, but rather claim that “each mating pair of metal bonding pads are in direct contact at grain boundaries” as recited on lines 4-5 of claims 1 and 14, and “direct contact of mating metal bonding pads at grain boundaries” on lines 4-5 of claim 21, and (b) therefore, one needs to know about the density, shape, size, direction/orientation and arrangement of the “grain boundaries” to determine whether the claim limitations “each mating pair of metal bonding pads are in direct contact at grain boundaries” and “direct contact of mating metal bonding pads at grain boundaries” are satisfied. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 and 21-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claims 1, 14 and 21, it is not clear what the “grain boundaries” recited on line 5 of claims 1, 14 and 21 imply and refer to, and what the characteristics such as the density, shape, size or width, direction/orientation and arrangement of the “grain boundaries” are, because (a) for “grain boundaries” to be formed, there should be a plurality of single crystalline grains in the first place, and for the arguments’ sake, the boundaries of the neighboring two or more single crystalline grains out of the plurality of single crystalline grains can then be referred to as “grain boundaries”, (b) therefore, it is not clear whether the term “grain boundaries” implies that the “mating pair of metal bonding pads” recited on lines 4-5 of claims 1, 14 and 21 comprise single crystalline metal grains, and it is not clear how the single crystalline metal grains can be formed since, unlike semiconductor materials whose atoms are bonded by covalent bonds, metallic atoms are bonded by metallic bonds, and thus single crystalline metals may not be well-defined, (c) also, it is not clear whether the term “grain boundaries” suggest that there are a plurality of grain boundaries with each of the grain boundaries being a closed-ended contact interface between two neighboring single crystalline grains since, as Fig. 2 of “Metal Microstructures in Four Dimensions: Characterization,” Encyclopedia of Materials: Science and Technology (2005) shows, most of the single crystalline grains are not in direct contact with each other, and therefore, each of the gaps between the single crystalline grains appears to be connected to form a contiguous, single and irregularly-shaped space or a single grain boundary rather than a plurality of grain boundaries, (d) while the term “grain boundaries” itself may be broadly interpreted, Applicants do not claim “grain boundaries” per se, but rather claim that “mating pair of metal bonding pads are in direct contact at grain boundaries” on lines 4-5 of claims 1, 14 and 21, and therefore, Applicants first need to claim what the “grain boundaries” refer to, and what their density, shape, size or width, direction/orientation and arrangement are, (e) if the Examiner may provide an analogy, the term “grain boundaries” is akin to a geographical relationship between South Korea and Japan, whose respective islands do not directly contact with each other, and therefore, it is not clear whether there is one boundary or there are a plurality of boundaries between South Korea and Japan, and (f) finally, due to the irregular shapes of the plurality of single crystal grains, it is highly likely that the actual physical contact areas of the plurality of single crystal grains would be points, and in this case, it is not clear whether the claimed “grain boundaries” refer to a plurality of contact points with zero dimension among the plurality of single crystal grains.
(2) Also regarding claims 1, 14 and 21, it is not clear what the limitation “mating pair of metal bonding pads are in direct contact at grain boundaries” on lines 4-5 of claims 1 and 14 and the limitation “direct contact of mating metal bonding pads at grain boundaries” recited on lines 4-5 of claim 21 suggest, because (a) as discussed above, the term “grain boundaries” implies empty spaces between single crystal grains, (b) therefore, logically “mating pair of metal bonding pads” cannot be “in direct contact at grain boundaries” since Applicants basically claim that two tangible objects of the “mating pair of metal bonding pads” are in direct contact with each other at the locations of empty spaces of the “grain boundaries”, and (c) it is not clear whether the limitation cited above suggests that the single crystalline grains of one of the mating pair of metal bonding pads and the single crystalline grains of the other of the mating pair of metal bonding pads are exactly the same in terms of their sizes or widths, distributions, locations, orientations, etc.
(3) Further regarding claims 1, 14 and 21, it is not clear what the “logical operations” recited on line 6 of claims 1, 14 and 21 refer to, because (a) for Applicants to claim that “the processor die comprises processing units for performing logical operations” or a plurality of logical operations, Applicants first need to claim what those plurality of “logical operations” are, (b) it is not clear whether “processing units” that can perform only one logical operation such as “AND” would read on the limitation “the processor die comprises processing units for performing logical operations”, (c) for example, if the “processing units” can perform a plurality of “AND” operations, it is not clear whether the “processing units” perform a plurality of logical operations, or the “processing units” perform only one logical operation multiple times.
(4) Regarding claims 1 and 21, it is not clear whether the limitation “the at least one memory die comprises at least two types of memory arrays” recited on lines 6-7 of claim 1, and the limitation “the at least three memory dies collectively comprise at least two different types of memory arrays” recited on lines 7-8 of claim 21 suggests that (i) one memory die can comprise two or more types of memory arrays, or (ii) one memory die comprises one type of memory arrays, another memory die comprises another type of memory arrays, a third memory die comprise yet another type of memory arrays, and so on, because depending on how the limitation cited above is interpreted, the claim limitation would be directed to very distinct configurations of the at least one memory die with distinct arrangements of the memory arrays.
(5) Still further regarding claims 1, 14 and 21, it is not clear what the limitation “bonding the bonded assembly to an interposer using a first array of solder material portions that is bonded to on-die bump structures of the processor die and to a first subset of first bump structures of the interposer (emphasis added)” recited on lines 11-13 of claims 1 and 14, and on lines 9-11 of claim 21 suggests, because (a) it is not clear whether “a first array of solder material portions” is not a part of the processor die since it appears that Applicants claim that, while the “on-die bump structures” are parts of the claimed processor die, “a first array of solder material portions” is not a part of the claimed processor die, and (b) in this case, it is not clear when “a first array of solder material portions” are formed, and where “a first array of solder material portions” is applied, i.e. it is not clear whether “a first array of solder material portions” is applied onto the interposer or onto “on-die bump structures of the processor die”.
(6) Still further regarding claims 1, 14 and 21, it is not clear what the limitation “bonding the bonded assembly to an interposer using a first array of solder material portions that is bonded to on-die bump structures of the processor die and to a first subset of first bump structures of the interposer (emphases added)” recited on lines 11-13 of claims 1 and 14, and on lines 9-11 of claim 21 suggests, because (a) it appears that Applicants claim that “a first array of solder material portions” is bonded to both the “on-die bump structures of the processor die and the “first subset of the first bump structures of the interposer, and (b) in this case, Applicants claim that a single array of solder material portions is bonded to two separate structures that belong to two separate elements, one being the processor die and the other being the interposer, which does not appear to make sense in that one needs at least two separately formed arrays of solder material portions to bond to the “on-die bump structures of the processor die” and the “first subset of first bump structures of the interposer”.
(7) Regarding claim 21, it is not clear what the limitation “intermetallic diffusion” recited on line 5 suggests, because (a) for Applicants to claim any kind of a diffusion, Applicants first need to claim which element or feature diffuses, (b) it is not clear whether the limitation “intermetallic diffusion” suggests that main constituents of the mating metal bonding pads diffuse into each other, or one of the constituents of the mating metal bonding pads diffuse into each other, and (c) furthermore, it is not clear whether the limitation “intermetallic diffusion” implies that the mating metal bonding pads are formed of different materials since, when the mating metal bonding pads are formed of the same material, there may not be any “intermetallic diffusion”.
(8) Further regarding claim 21, it is not clear whether the “intermetallic diffusion” recite on line 5 is an inherent characteristic of bonding of “the mating metal bonding pads”, or there should be an additional process to cause the “intermetallic diffusion” such as thermal treatment, because (a) Applicants do not specifically claim what the “intermetallic diffusion” refers to, and (b) therefore, it is not clear whether one atom from one mating metal bonding pad and another atom from another mating metal bonding pad swapping their positions would read on the “intermetallic diffusion”.
Claims 2-13 depend on claim 1, claims 15 and 16 depend on claim 14, and claims 22-24 depend on claim 21, and therefore, claims 2-13, 15, 16 and 22-24 are also indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8 and 14-16, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2020/0135677) in view of Tsai et al. (US 11,164,754)
Regarding claim 1, Chang et al. disclose a method of forming a device structure (Fig. 23), comprising: bonding a processor die (71) ([0041]) with at least one memory die (die including integrated circuit devices 26 and HBM cubes or memory dies) ([0022] and [0052]), wherein each vertically neighboring pair of dies among the processor die and the at least one memory die is bonded to each other by performing a respective metal-to-metal bonding process (Figs. 20 and 21) ([0049]) in which each mating pair of metal bonding pads (56 and 108 in Fig. 20) ([0029] and [0049]) are in direct contact at grain boundaries, because this limitation is indefinite as discussed above under 35 USC 112(b) rejections, wherein the processor die comprises processing units (80 and/or 81 in Fig. 23) ([0052]) for performing logical operations, because this limitation is also indefinite as discussed above under 35 USC 112(b) rejections, and wherein the at least one memory die comprises at least two types of memory arrays (HBM in [0052]) selected from a static random access memory array, a gain cell random access memory array, and magnetoresistive random access memory array, and a resistive random access memory array, because this limitation is also indefinite as discussed above under 35 USC 112(b) rejections, whereby a bonded assembly of the processor die (71) and the at least one memory die (die including integrated circuit devices 26 and HBM cubes or memory dies) is formed, see Fig. 22; and bonding the bonded assembly to an interposer (118) ([0052]) using a first array of solder material portions (86) ([0042]) that is bonded to on-die bump structures of the processor die (element corresponding to UBM 84s shown in Fig. 11) ([0042]).
Chang et al. differ from the claimed invention by not showing that the first array of solder material portions is also bonded to a first subset of first bump structures of the interposer.
Tsai et al. disclose an interposer (Fig. 7) (col. 3, lines 32-33) comprising first bump structures (upper 124 or 126).
Since both Chang et al. and Tsai et al. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first array of solder material portions can also be bonded to a first subset of first bump structures of the interposer, because (a) Chang et al. disclose in paragraph [0052] that “FIG. 23 further illustrates the bonding of package 116 to package component 118, which may be a printed circuit board, an interposer, a package substrate, or the like”, and therefore, Chang et al. do not show a detailed structure of the package component 118 when the package component 118 is an interposer, and (b) as disclosed by Tsai et al., it has been well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that an interposer commonly comprises bump structures for an electrical connection to a semiconductor device.
Regarding claims 2 and 5-8, Chang et al. in view of Tsai et al. differ from the claimed invention by not showing that each of the at least one memory die comprises a respective set of memory address input nodes; and the processor die comprises a unified memory controller unit including a set of memory address output nodes that are electrically connected to each set of memory address input nodes within the at least one memory die (claim 2), wherein the unified memory controller unit is configured to access each memory element within the at least two types of memory arrays through selection of bit values of a memory address that is transmitted to the set of memory address output nodes (claim 5), wherein: the unified memory controller unit includes a set of data input nodes; each of the at least one memory die comprises a respective set of data output nodes that is electrically connected to the set of data input nodes; and the unified memory controller unit is configured to receive data stored in any memory element within the at least two types of memory arrays through the set of data input nodes (claim 6), one the at least one memory die comprises a plurality of types of memory dies; and the unified memory controller unit is configured to access each type of memory array selected from the plurality of types of memory dies (claim 7), and memory latencies are different from the at least two types of memory arrays; and the unified memory controller unit is configured to sequentially address two different types of memory arrays selected from the at least two types of memory arrays and to sequentially receive two sets of data stored in the two different types of memory arrays with a temporal offset using a same set of data input nodes (claim 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that each of the at least one memory die can comprise a respective set of memory address input nodes; and the processor die can comprise a unified memory controller unit including a set of memory address output nodes that are electrically connected to each set of memory address input nodes within the at least one memory die, wherein the unified memory controller unit can be configured to access each memory element within the at least two types of memory arrays through selection of bit values of a memory address that is transmitted to the set of memory address output nodes, wherein: the unified memory controller unit can include a set of data input nodes; each of the at least one memory die comprises a respective set of data output nodes that is electrically connected to the set of data input nodes; and the unified memory controller unit can be configured to receive data stored in any memory element within the at least two types of memory arrays through the set of data input nodes, one the at least one memory die can comprise a plurality of types of memory dies; and the unified memory controller unit can be configured to access each type of memory array selected from the plurality of types of memory dies, and memory latencies can be different from the at least two types of memory arrays; and the unified memory controller unit can be configured to sequentially address two different types of memory arrays selected from the at least two types of memory arrays and to sequentially receive two sets of data stored in the two different types of memory arrays with a temporal offset using a same set of data input nodes, because (a) the claimed configurations of the at least one memory die and the processor die are commonly employed configurations of memory dies and processor dies in manufacturing semiconductor memory devices, and (b) Applicants’ inventive concept is not exactly directed to manufacturing new types of memory devices, but rather is directed to bonding preexisting, well-known and/or commercially available memory devices in a manner Applicants designed.
Regarding claim 3, Chang et al. in view of Tsai et al. differ from the claimed invention by not showing that the at least one memory die comprises at least two memory dies that are directly bonded for each vertically neighboring pair thereamongst by metal-to-metal bonding.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the at least one memory die comprises at least two memory dies that are directly bonded for each vertically neighboring pair thereamongst by metal-to-metal bonding, because the claimed configuration and arrangement of at least two memory dies are commonly employed configuration and arrangement of HBM disclosed by Chang et al.
Please refer to the explanations of the corresponding limitations above.
Regarding claim 14, Chang et al. disclose a method of forming a device structure (Fig. 23), comprising: bonding a processor die (71) with multiple memory dies (die including 22), wherein each vertically neighboring pair of dies among the processor die and the multiple memory dies is bonded to each other by performing a respective metal-to-metal bonding process (Figs. 20 and 21) in which each mating pair of metal bonding pads (56 and 108 in Fig. 20) are in direct contact at grain boundaries, because this limitation is indefinite as discussed above under 35 USC 112(b) rejections, wherein the processor die comprises processing units for performing logical operations, because this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and wherein the multiple memory dies (HBM cubes) comprise at least one type of memory array selected from a gain cell random access memory array, and magnetoresistive random access memory array, and a resistive random access memory array, whereby a bonded assembly of the processor die and at least one memory die is formed (Fig. 23); and bonding the bonded assembly to an interposer (118 in Fig. 23) using a first array of solder material portions that is bonded to on-die bump structures of the processor die.
Chang et al. differ from the claimed invention by not showing that the first array of solder material portions is also bonded to a first subset of first bump structures of the interposer.
Tsai et al. disclose an interposer (Fig. 7) (col. 3, lines 32-33) comprising first bump structures (upper 124 or 126).
Since both Chang et al. and Tsai et al. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first array of solder material portions can also be bonded to a first subset of first bump structures of the interposer, because (a) Chang et al. disclose in paragraph [0052] that “FIG. 23 further illustrates the bonding of package 116 to package component 118, which may be a printed circuit board, an interposer, a package substrate, or the like”, and therefore, Chang et al. do not show a detailed structure of the package component 118 when the package component 118 is an interposer, and (b) as disclosed by Tsai et al., it has been well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that an interposer commonly comprises bump structures for an electrical connection to a semiconductor device.
Regarding claims 15 and 16, Chang et al. in view of Tsai et al. differ from the claimed invention by not showing that each of the multiple memory dies comprises a respective set of memory address input nodes; and the processor die comprises a unified memory controller unit including a set of memory address output nodes that are electrically connected to each set of memory address input nodes within the at least one memory die (claim 15), wherein: the unified memory controller unit includes a set of data input nodes; each of the multiple memory dies comprises a respective set of data output nodes that is electrically connected to the set of data input nodes; and the unified memory controller unit is configured to receive data stored in any memory element within the at least two types of memory arrays through the set of data input nodes (claim 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that each of the at least one memory die can comprise a respective set of memory address input nodes; and the processor die can comprise a unified memory controller unit including a set of memory address output nodes that are electrically connected to each set of memory address input nodes within the at least one memory die, wherein: the unified memory controller unit can include a set of data input nodes; each of the multiple memory dies comprises a respective set of data output nodes that is electrically connected to the set of data input nodes; and the unified memory controller unit can be configured to receive data stored in any memory element within the at least two types of memory arrays through the set of data input nodes, because (a) the claimed configurations of the at least one memory die and the processor die are commonly employed configurations of memory dies and processor dies in manufacturing semiconductor memory devices, and (b) Applicants’ inventive concept is not exactly directed to manufacturing new types of memory devices, but rather is directed to bonding preexisting, well-known and/or commercially available memory devices in a manner Applicants designed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Uzoh et al. (US 2025/0006674)
Nad et al. (US 11,177,234)
Rosch et al. (US 11,769,719)
Jezewski et al. (US 2025/0309100)
Haba (US 12,642,110)
Zaidy et al. (US 12,112,793)
Uzoh (US 2024/0222315)
Zhao et al. (US 2024/0217210)
Theil et al. (US 2024/0213191)
Mirkarimi et al. (US 2022/0285303)
Tsai et al. (US 9,728,521)
Haba et al. (US 12,543,577)
Kim et al. (US 12,557,712)
Aleksov et al. (US 12,550,768)
Chidambaram et al. (US 2024/0332237)
Madan et al. (WO 2024/049862)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM-6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-2435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J.K./Primary Examiner, Art Unit 2815 July 9, 2026
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