DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 16, 2026 has been entered.
Response to Amendment
This Office Action is in response to the Request for Continued Examination filed on the date: September 16, 2026.
Claims 1-2 and 4-22 are currently pending. Claims 1-2, 4-6, 8 and 10-12 have been amended. Claim 3 has been canceled. Claims 21-22 are new.
Response to Arguments
Anticipation Rejections
Applicant’s arguments with respect to claim(s) 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 1 is objected to because of the following informalities: This claim recites the limitation “a first terminal electrically coupled a gate” in line 4. This limitation appears to be missing a “to” between “coupled” and “a gate” and should be amended to “a first terminal electrically coupled to a gate”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asam US2019/0056448 (previously cited), in view of Reedy et al. US2024/0110966 (called Reedy hereinafter and previously cited) and further in view of Majerus et al. US2025/0199053 (called Majerus hereinafter and newly cited).
Regarding independent claim 11, Asam teaches a method (Abstract), comprising:
charging a gate of a transistor (Figs. 4 and 7; para [0054]; transistors 42), wherein the transistor includes the gate and a source and a drain (para [0029-0030]);
terminating the charging of the gate of the transistor (Figs. 4 and 7; para [0054]; open switch 46);
comparing a gate voltage of the gate to a detection voltage (Figs. 4 and 7; para [0058]; window comparator 49) at or after terminating the charging of the gate of the transistor (para [0054]); and
determining whether or not the transistor has a defect based at least in part on comparing the gate voltage of the gate to the detection voltage (para [0060]; various fault states may be detected based on the output of window comparator 49).
Asam fails to teach wherein, during determining, the gate of the transistor is in a high impedance state.
Reedy teaches wherein, during determining, the gate of the transistor is in a high impedance state (Fig. 2A; para [0022]; during testing of gate defects of the transistor T, the bias circuit is disconnected from the transistor by opening switches S1a and S1b, thus placing the transistor in a high impedance state, and closing switch S2 so the voltage detector can measure the gate voltage/current).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the method as described by Asam with the gate defect testing as described by Reedy for the purpose of determining when leakage currents occur in a gate of a transistor in both a test environment and in a field environment (para [0007]).
Asam and Reedy fail to teach determining is performed for a detection time period of at least 1 ms.
Majerus teaches determining is performed for a detection time period of at least 1 ms (Fig. 11; para [0091-0093]; measurement performed over 500 ms).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the structure as described by Asam and Reedy with the measurement time period as described by Majerus for the purpose of determine the thermal resistance characteristic of a transistor (para [0093]).
Regarding claim 12, Asam, Reedy and Majerus teach the method of claim 11, Asam further teaches wherein determining whether or not the transistor has the defect comprises determining whether the gate voltage on the gate of the transistor reaches at least the detection voltage at or within a detection time period (Figs. 4, 5A and 5B; para [0060]).
Regarding claim 13, Asam, Reedy and Majerus teach the method of claim 12, Asam further teaches further comprising: placing the source of the transistor at a source voltage, wherein when terminating the charging of the gate of the transistor, the detection voltage is between the source voltage and the gate voltage (Figs. 4, 5A and 5B; para [0058]).
Allowable Subject Matter
Claims 1-2, 4-10 and 14-22 are indicated as allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 1, the prior arts of record taken alone or in combination fail to teach or suggest:
“opening a gate driver switch having a first terminal electrically coupled to a gate driver and a second terminal electrically coupled to a node; opening a gate access switch having a first terminal electrically coupled a gate of a transistor and a second terminal electrically coupled to the node, closing a reset switch electrically coupled to the gate of the transistor such that the gate is at a first voltage, wherein the transistor includes a drain, the gate, and a source, and the source is electrically coupled to a first voltage supply, wherein closing the reset switch is performed after opening the gate driver switch and opening the gate access switch,” when used in combination with all other limitations of claim 1.
Claims 2, 4-10 and 21-22 are indicated as allowable subject matter for depending on claim 1.
Regarding independent claim 14, this claim was indicated as allowable subject matter in the previous Office Action mailed on May 05, 2026.
Claims 15-20 are indicated as allowable subject matter for depending on claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Marques Martins et al. discloses “Evaluating a gate-source leakage current in a transistor device” (see US2019/0101585)
Hirose discloses “Voltage detecting circuit and method for measuring characteristic of transistor” (see US2014/0139206)
Odagiri discloses “Brake driving control circuit and breakdown detection method thereof” (see US2020/0313578)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID B FREDERIKSEN whose telephone number is (571)272-8152. The examiner can normally be reached M-F 8am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID B FREDERIKSEN/Examiner, Art Unit 2858
/GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 9/28/2026
