DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the Amendment filed on the date: May 28, 2026.
Claims 1-20 are currently pending. Claims 1, 11, 19 and 20 have been amended. No claims have been cancelled or are new.
Response to Arguments
Anticipation Rejections
Applicant’s arguments with respect to claim(s) 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asam US2019/0056448 (previously cited) in view of Reedy et al. US2024/0110966 (called Reedy hereinafter and newly cited).
Regarding independent claim 1, Asam teaches a method (Abstract), comprising:
closing a reset switch (Figs. 4 and 7; switch 46) electrically coupled to a gate of a transistor (Figs. 4 and 6; gate of transistors 42) such that the gate is at a first voltage (para [0054]), wherein the transistor includes a drain, the gate, and a source (para [0029-0030]), and the source is electrically coupled to a first voltage supply (Figs. 4 and 7; Vbat is electrically coupled to the source of transistors 42);
opening the reset switch (Figs. 4 and 7; para [0054]; open switch 46);
closing a comparator switch (Figs. 4 and 7; closing switch 47 when switch 46 is opened) such that the gate is electrically coupled to a first input terminal of a voltage comparator (Figs. 4 and 7; window comparator 49), wherein a second input terminal of the voltage comparator is adapted to receive a detection voltage (Figs. 4 and 7; para [0058]); and
determining whether or not the transistor has a defect based at least in part on an output from the voltage comparator (para [0060]; various fault states may be detected based on the output of window comparator 49).
Asam fails to teach wherein, during determining, the gate of the transistor is not electrically connected to a power source.
Reedy teaches wherein, during determining, the gate of the transistor is not electrically connected to a power source (Fig. 2A; para [0022]; during testing of gate defects of the transistor T, the bias circuit is disconnected from the transistor by opening switches S1a and S1b and closing switch S2 so the voltage detector can measure the gate voltage/current).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the method as described by Asam with the gate defect testing as described by Reedy for the purpose of determining when leakage currents occur in a gate of a transistor in both a test environment and in a field environment (para [0007]).
Regarding claim 2, Asam and Reedy teach the method of claim 1, Asam further teaches further comprising: placing the gate of the transistor in a high impedance state before closing the reset switch (para [0056]; transistors 42 are off).
Regarding claim 3, Asam and Reedy teach the method of claim 2, Asam further teaches wherein placing the gate of the transistor in the high impedance state comprises opening a gate access switch between a gate driver and the gate of the transistor (Fig. 7; switch 71 is opened to not charge the gate of transistors 42).
Regarding claim 4, Asam and Reedy teach the method of claim 1, Asam further teaches further comprising: closing a gate access switch (Fig. 7; switch 71) such that a signal from a gate driver (Fig. 7; charge pump 43) is received by the gate of the transistor to turn on the transistor.
Regarding claim 5, Asam and Reedy teach the method of claim 4, Asam further teaches wherein after closing the gate access switch (Fig. 7; switch 71), a voltage of the drain of the transistor is substantially the same as a voltage of the source of the transistor (Fig. 7; turning on the transistors 42 will result in the voltage at the top/drain of the transistors to be at Vbat and the voltage at the bottom/source of the transistors to see about Vbat as well).
Regarding claim 6, Asam and Reedy teach the method of claim 4, Asam further teaches wherein: determining whether or not the transistor has a defect results in no defect detected (para [0060]), and closing the gate access switch is performed in response to no defect being detected (Figs. 4 and 7; para [0054]; switch 71 would be closed to continue testing of transistors 42).
Regarding claim 7, Asam and Reedy teach the method of claim 6, Asam further teaches wherein a load or test equipment is electrically coupled to the transistor (Figs. 4 and 7; Rload 412).
Regarding claim 8, Asam and Reedy teach the method of claim 6, Asam further teaches wherein determining whether or not the transistor has the defect comprises: determining whether a gate voltage on the gate of the transistor reaches at least the detection voltage at or within a detection time period (Figs. 5A and 5B; para [0060]; detection time period of Δt for detection of voltage at the gate of the transistors 42).
Regarding claim 9, Asam and Reedy teach the method of claim 8, but fails to teach wherein determining whether or not the transistor has the defect is performed such that the detection time period is at most 0.9 s.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the method as described by Asam and Reedy to have wherein determining whether or not the transistor has the defect is performed such that the detection time period is at most 0.9 s. Asam teaches that a time duration is used with a voltage between two voltage thresholds to determine if fault states are detected (see paragraph [0060]). The time duration is not explicitly stated, but the time duration varies based on how many transistors are faulting and in the case of if both transistors are faulting then the time duration will be very small (see paragraph [0060]). Thus, one skilled in the art would be able to have the time duration to determine a fault in the transistors to be at most 0.9 seconds for the purpose of quickly determining if the transistor(s) are faulty to then replace them before any potential damage occurs to the components associated with the transistor(s).
Regarding claim 10, Asam and Reedy teach the method of claim 1, Asam further teaches wherein: determining whether or not the transistor has a defect results in the defect being detected (para [0060]), and keeping a gate access switch open in response to the defect being detected (Figs. 4 and 7; para [0054]; switch 71 would be open to prevent a defective transistor from operating).
Regarding independent claim 11, Asam teaches a method (Abstract), comprising:
charging a gate of a transistor (Figs. 4 and 7; para [0054]; transistors 42), wherein the transistor includes the gate and a source and a drain (para [0029-0030]);
terminating the charging of the gate of the transistor (Figs. 4 and 7; para [0054]; open switch 46);
comparing a gate voltage of the gate to a detection voltage (Figs. 4 and 7; para [0058]; window comparator 49) at or after terminating the charging of the gate of the transistor (para [0054]); and
determining whether or not the transistor has a defect based at least in part on comparing the gate voltage of the gate to the detection voltage (para [0060]; various fault states may be detected based on the output of window comparator 49).
Asam fails to teach wherein, during determining, the gate of the transistor is in a high impedance state.
Reedy teaches wherein, during determining, the gate of the transistor is in a high impedance state (Fig. 2A; para [0022]; during testing of gate defects of the transistor T, the bias circuit is disconnected from the transistor by opening switches S1a and S1b, thus placing the transistor in a high impedance state, and closing switch S2 so the voltage detector can measure the gate voltage/current).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the method as described by Asam with the gate defect testing as described by Reedy for the purpose of determining when leakage currents occur in a gate of a transistor in both a test environment and in a field environment (para [0007]).
Regarding claim 12, Asam and Reedy teach the method of claim 11, Asam further teaches wherein determining whether or not the transistor has the defect comprises determining whether the gate voltage on the gate of the transistor reaches at least the detection voltage at or within a detection time period (Figs. 4, 5A and 5B; para [0060]).
Regarding claim 13, Asam and Reedy teach the method of claim 12, Asam further teaches further comprising: placing the source of the transistor at a source voltage, wherein when terminating the charging of the gate of the transistor, the detection voltage is between the source voltage and the gate voltage (Figs. 4, 5A and 5B; para [0058]).
Allowable Subject Matter
Claims 14-20 are indicated as allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 14, this claim was indicated as allowable subject matter in the previous Office Action mailed on May 05, 2026.
Claims 15-20 are indicated as allowable subject matter for depending on claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wortberg discloses “Monitoring device and monitoring method” (see US2017/0336475)
Tiew et al. discloses “Methods and apparatus to test power transistors” (see US7511527)
Hartman et al. discloses “Systems and methods for testing power transistors” (see US8427331)
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID B FREDERIKSEN whose telephone number is (571)272-8152. The examiner can normally be reached M-F 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID B FREDERIKSEN/Examiner, Art Unit 2858
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858
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