DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (correctly identified by the Applicant as corresponding to claims 1-8) in the reply filed on 6/22/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Wu et al (US 2022/0102397).
1. (original) A method, comprising:
providing a main body of a complementary metal oxide semiconductor image sensor (Fig.1 and [0003]);
forming a plurality of trenches (Fig.1 (111) and [0014/0017]) in a back side of the main body, each of the plurality of trenches comprising a set of sidewalls and a base extending between the set of sidewalls (Fig.1 (111) and [0017]);
performing a plasma treatment [0038] to form a doped layer (Fig.1-2/14 (114) and [0038]) along the base and along each of the set of sidewalls (Fig.1-2/14 (114) and [0038]);
performing a thermal treatment to the back side of the main body [0036-thermal treatment is performed when forming the dielectric layer 1302/0041-0042- thermal treatment for dopants]; and
forming a dielectric layer (Fig.1-2/13 (112/1302- dielectrics are over 114) and [0043/0036]) over the doped layer (Fig.1-2/13 (114) and [0038]) following the thermal treatment [0036/0042].
2. (original) The method of claim 1, further comprising forming a high-k dielectric layer (Fig.2/14 (113) and 0043]) over the dielectric layer (Fig.13 (1302) and [0036]).
3. (original) The method of claim 1, wherein the thermal treatment is a dynamic surface annealing process performed at a temperature greater than 600°C and for a time duration between 250 microseconds and 1 millisecond [0042].
4. (original) The method of claim 1, wherein the thermal treatment is a rapid thermal anneal performed at a temperature between 400°C and 450°C and for a time duration between 30 minutes and 60 minutes [0042].
5. (original) The method of claim 1, wherein the plasma treatment comprises directing diborane ions into the plurality of trenches [0038].
6. (original) The method of claim 1, wherein forming the dielectric layer comprises one of: performing a rapid thermal oxidation process, and performing a chemical oxidation process [0043].
7. (Currently Amended) The method of claim 1, further comprising forming a sacrificial oxide within the plurality of trenches prior to performing the plasma treatment (Fig.13 (1302) and [0036]) .
8. (original) The method of claim 1, further comprising forming a reflective filler within the plurality of trenches after the dielectric layer is formed (Fig.1-2 (116) and [0019- both fill and color filter are silicon dioxide and are reflective]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chiang et al (US 2019/0096939); (US 10304886); and Lee et al (US 2018/0301502) teach similar methods regarding backside trenches for CMOS image sensor applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
7/11/26
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