Attorney’s Docket Number: 18506-1797US2
Filing Date: 04/29/2024
Claimed Priority Date: 08/18/2020 (DIV of 16/996,834 now PAT 12,002,766)
Applicant(s): Huang et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 07/01/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 3 (drawn to Figs. 3C and 19-20), in the reply filed on 07/01/2026, is acknowledged. Applicant cancelled claims 1-9 and 19, added new claims 21-30, and indicated that claims 10-18 and 20-30 read on the elected Species. The examiner agrees. Accordingly, pending in this application are claims 10-18 and 20-30.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10, 23, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US10,276,449).
Regarding Claim 10, Wu (see, e.g., Figs. 3-13) shows all aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- receiving a substrate having fin structures (e.g., substrate 200 having fins 210), wherein the substrate comprises a material having a substrate thermal expansion coefficient (see, e.g., Col. 2, L. 40-60: 200 of silicon material) (see, e.g., Figs. 3-4)
- forming a first dielectric material (e.g., dielectric 212) over the substrate and the fin structures, the first dielectric material having a first thermal expansion coefficient (see, e.g., Col. 3, L. 30-33: 212 of silicon nitride material) (see, e.g., Fig. 5)
- forming a second dielectric material (e.g., dielectric 214) over the first dielectric material, the second dielectric material having a second thermal expansion coefficient (see, e.g., Col. 3, L. 30-33: 214 of silicon oxide) (see, e.g., Fig. 6)
- removing a portion of the first dielectric material and a portion of the second dielectric material together to form an isolation structure between the fin structures (see, e.g., Figs. 7-13: 212 and 214 are partially removed together, by CMP and etching, to form isolation structures 212,214a between fins 210)
Regarding Claim 23, Wu (see, e.g., Figs. 3-13) shows all aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- receiving a substrate having a fin structure and a trench adjacent to the fin structure (e.g., substrate 200 having fins 210 and trenches therebetween) (see, e.g., Figs. 3-4)
- conformally forming a first dielectric material (e.g., dielectric 212) over the substrate, the trench and the fin structures, the first dielectric material having a first thermal expansion coefficient (see, e.g., Col. 3, L. 30-33: 212 of silicon nitride material) (see, e.g., Fig. 5)
- forming a second dielectric material (e.g., dielectric 214) over the first dielectric material to fill the trench, the second dielectric material having a second thermal expansion coefficient (see, e.g., Col. 3, L. 30-33: 214 of silicon oxide) (see, e.g., Fig. 6)
- removing a portion of the first dielectric material and a portion of the second dielectric material together to form an isolation structure in the trench (see, e.g., Figs. 7-13: 212 and 214 are partially removed together, by CMP and etching, to form isolation structures 212,214a between fins 210)
Regarding Claim 26, Wu (see, e.g., Figs. 12-13) shows that the fin structure (e.g., 210) is exposed through the isolation structure (e.g., 212,214a).
Claims 10, 12, 14-16, 23, 26-28, and 30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US2020/0357703).
Regarding Claim 10, Lee (see, e.g., Figs. 1-5) shows all aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- receiving a substrate having fin structures (e.g., substrate 102 having fins 202), wherein the substrate comprises a material having a substrate thermal expansion coefficient (see, e.g., Par. [0031]: 102 of silicon material) (see, e.g., Figs. 1-2)
- forming a first dielectric material (e.g., dielectric 306) over the substrate and the fin structures, the first dielectric material having a first thermal expansion coefficient (see, e.g., Par. [0044]: 306 of silicon nitride material) (see, e.g., Fig. 3)
- forming a second dielectric material (e.g., dielectric 402) over the first dielectric material, the second dielectric material having a second thermal expansion coefficient (see, e.g., Par. [0047]: 402 of silicon oxide material) (see, e.g., Fig. 4)
- removing a portion of the first dielectric material and a portion of the second dielectric material together to form an isolation structure between the fin structures (see, e.g., Par. [0048]-[0050]: 306 and 402 are partially removed together, by CMP and etching, to form STI structures 502 between fins 202) (see, e.g., Fig. 5)
Regarding Claim 12, Lee (see, e.g., Fig. 3 and Par. [0039]-[0043]) shows forming a dielectric liner (e.g., liner 304 of aluminum oxide) over the substrate and the fin structures before the forming of the first dielectric material.
Regarding Claim 14, Lee (see, e.g., Fig. 5) shows that the fin structures (e.g., 202) are exposed from the dielectric liner (e.g., 304).
Regarding Claim 15, Lee (see, e.g., Fig. 5) shows that the dielectric liner (e.g., 304) and the first dielectric material (e.g., 306) respectively has an U-shape.
Regarding Claim 16, Lee (see, e.g., Fig. 5) shows that a topmost surface of the dielectric liner (e.g., 304), a topmost surface of the first dielectric material (e.g., 306) and a top surface of the second dielectric material (e.g., 402) are level with each other.
Regarding Claim 23, Lee (see, e.g., Figs. 1-5) shows all aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- receiving a substrate having a fin structure and a trench adjacent to the fin structure (e.g., substrate 102 having fins 202 and trenches therebetween) (see, e.g., Figs. 1-2)
- conformally forming a first dielectric material (e.g., dielectric 306) over the substrate, the trench and the fin structures, the first dielectric material having a first thermal expansion coefficient (see, e.g., Par. [0044]: 306 of silicon nitride material) (see, e.g., Fig. 3)
- forming a second dielectric material (e.g., dielectric 402) over the first dielectric material to fill the trench, the second dielectric material having a second thermal expansion coefficient (see, e.g., Par. [0047]: 402 of silicon oxide material) (see, e.g., Fig. 4)
- removing a portion of the first dielectric material and a portion of the second dielectric material together to form an isolation structure in the trench (see, e.g., Par. [0048]-[0050]: 306 and 402 are partially removed together, by CMP and etching, to form STI structures 502 between fins 202) (see, e.g., Fig. 5)
Regarding Claim 26, Lee (see, e.g., Fig. 5) shows that the fin structure (e.g., 202) is exposed through the isolation structure (e.g., 502).
Regarding Claim 27, Lee (see, e.g., Fig. 3 and Par. [0039]-[0043]) shows forming a dielectric liner (e.g., liner 304 of aluminum oxide) over the substrate, the trench and the fin structure prior to the forming of the first dielectric material.
Regarding Claim 28, Lee (see, e.g., Fig. 5) shows that the fin structure (e.g., 202) is exposed through the dielectric liner (e.g., 304).
Regarding Claim 30, Lee (see, e.g., Par. [0043]-[0044]) discloses that 304 may have a thickness of approximately 0.5 nm to approximately 1.5 nm, and that 306 may have a thickness of approximately 1 nm to approximately 10 nm. Therefore, Lee also shows that a thickness of the dielectric liner (e.g., 304) is less than a thickness of the first dielectric material (e.g., 304 having 0.5 nm vs. 306 having 10 nm).
Claims 10, 12, 14, 17, 21-23, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bi et al. (US9,691,765).
Regarding Claim 10, Bi (see, e.g., Figs. 1-8) shows all aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- receiving a substrate having fin structures (e.g., substrate 5 having fins 10,15), wherein the substrate comprises a material having a substrate thermal expansion (see, e.g., Fig. 1)
- forming a first dielectric material (see, e.g., Col. 9, L. 41 to Col. 10, L. 9: dielectric 40a,b) over the substrate and the fin structures, the first dielectric material having a first thermal expansion coefficient (see, e.g., Fig. 4)
- forming a second dielectric material (see, e.g., Col. 10, L. 36-59: dielectric 50) over the first dielectric material, the second dielectric material having a second thermal expansion coefficient (see, e.g., Fig. 5)
- removing a portion of the first dielectric material and a portion of the second dielectric material together to form an isolation structure between the fin structures (see, e.g., Col. 10, L. 60-67: 40a,b and 50 are partially removed together, to form isolation stacks between fins) (see, e.g., Fig. 6)
Regarding Claim 12, Bi (see, e.g., Fig. 1 and Col. 8, L. 4-22) shows forming a dielectric liner (e.g., dielectric liner 31) over the substrate and the fin structures before the forming of the first dielectric material.
Regarding Claim 14, Bi (see, e.g., Fig. 8) shows that the fin structures (e.g., 10,15) are exposed from the dielectric liner (e.g., 31).
Regarding Claim 17, Bi (see, e.g., Figs. 1-8) shows all aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- forming a first trench (e.g., trench in device region 25 having a depth H2) and a second trench (e.g., trench in device region 20 having a depth H1) in a substrate (see, e.g., Col. 5, L. 46-65: substrate 5 can be a bulk substrate from which fins 10 and 15 are formed), wherein a depth of the first trench is greater than a depth of the second trench, and the first trench and the second trench are separated from each other by a fin structure (e.g., fin 10) (see, e.g., Fig. 1)
- forming a dielectric liner (e.g., dielectric liner 31) in the first trench and the second trench (see, e.g., Fig. 1)
- forming a first dielectric material (see, e.g., Col. 8, L. 23-39: dielectric 30a,b) over the dielectric liner in the first trench and the second trench, wherein the first dielectric material has a first thermal expansion coefficient (see, e.g., Fig. 1)
- forming a second dielectric material (see, e.g., Col. 9, L. 41 to Col. 10, L. 9: dielectric 40a,b) over the first dielectric material in the first trench and the second trench, wherein the second dielectric material has a second thermal expansion coefficient (see, e.g., Fig. 4)
- recessing the second dielectric material to form a first isolation structure in the first trench and a second isolation structure in the second trench (see, e.g., Col. 10, L. 60-67: 40a,b is recessed to define isolation stack 30b,40b,50 and 30a,40a respectively) (see, e.g., Fig. 6)
Regarding Claim 21, Bi (see, e.g., Fig. 1) shows that a width of the first trench (e.g., trench in 25) is greater than a width of the second trench (e.g., trench in 20).
Regarding Claim 22, Bi (see, e.g., Fig. 1) shows that a bottommost surface of the dielectric liner (e.g., 31) in the first trench (e.g., trench in 25) and a bottommost surface of the dielectric liner in the second trench (e.g., trench in 20) are at different levels.
Regarding Claim 23, Bi (see, e.g., Figs. 1-8) shows all aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- receiving a substrate having a fin structure and a trench adjacent to the fin structure (see, e.g., Col. 5, L. 46-65: substrate 5 can be a bulk substrate from which fins 10 and 15 are formed with trenches therebetween) (see, e.g., Fig. 1)
- conformally forming a first dielectric material (see, e.g., Col. 8, L. 4-22: dielectric 31 is typically formed by a conformal deposition process) over the substrate, the trench and the fin structures, the first dielectric material having a first thermal expansion coefficient (see, e.g., Fig. 1)
- forming a second dielectric material (see, e.g., Col. 8, L. 23-39: dielectric 30a,b) over the first dielectric material to fill the trench, the second dielectric material having a second thermal expansion coefficient (see, e.g., Fig. 1)
- removing a portion of the first dielectric material and a portion of the second dielectric material together to form an isolation structure in the trench (see, e.g., Col. 8, L. 63 to Col. 9, L. 10: 31 and 30a,b are partially removed together, to form isolation stacks between fins) (see, e.g., Fig. 2)
Regarding Claim 26, Bi (see, e.g., Fig. 2) shows that the fin structure (e.g., 10 or 15) is exposed through the isolation structure.
Claims 10, 23, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo et al. (US2019/0097056).
Regarding Claim 10, Kuo (see, e.g., Figs. 14-16) shows all aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- receiving a substrate having fin structures (e.g., substrate 100 having fins 160,170), wherein the substrate comprises a material having a substrate thermal expansion coefficient (see, e.g., Par. [0011]: 100 of silicon material) (see, e.g., Fig. 14)
- forming a first dielectric material (e.g., dielectric 192) over the substrate and the fin structures, the first dielectric material having a first thermal expansion coefficient (see, e.g., Par. [0054]: dielectric 192 of silicon nitride material) (see, e.g., Fig. 16)
- forming a second dielectric material (e.g., dielectric 200) over the first dielectric material, the second dielectric material having a second thermal expansion coefficient (see, e.g., Par. [0054]: 200 of silicon oxide material) (see, e.g., Fig. 16)
- removing a portion of the first dielectric material and a portion of the second dielectric material together to form an isolation structure between the fin structures (see, e.g., Par. [0054]: 192 and 200 are partially removed together, by CMP and recessing, to form STI structures between fins) (see, e.g., Fig. 16)
Regarding Claim 23, Kuo (see, e.g., Figs. 14-16) shows all aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- receiving a substrate having a fin structure and a trench adjacent to the fin structure (e.g., substrate 100 having fins 160,170 and trenches therebetween) (see, e.g., Fig. 14)
- conformally forming a first dielectric material (e.g., dielectric 192) over the substrate, the trench and the fin structures, the first dielectric material having a first thermal expansion coefficient (see, e.g., Par. [0054]: dielectric 192 of silicon nitride material) (see, e.g., Fig. 16)
- forming a second dielectric material (e.g., dielectric 200) over the first dielectric material to fill the trench, the second dielectric material having a second thermal expansion coefficient (see, e.g., Par. [0054]: 200 of silicon oxide material) (see, e.g., Fig. 16)
- removing a portion of the first dielectric material and a portion of the second dielectric material together to form an isolation structure in the trench (see, e.g., Par. [0054]: 192 and 200 are partially removed together, by CMP and recessing, to form STI structures between fins) (see, e.g., Fig. 16)
Regarding Claim 26, Kuo (see, e.g., Fig. 16) shows that the fin structure (e.g., 160,170) is exposed through the isolation structure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11 and 24-25 are rejected under 35 U.S.C. 103 as obvious over Wu et al. (US10,276,449) in view of NPL “Coefficient of Thermal Expansion (CTE)” (hereinafter NPL CTE).
Regarding Claim 11, Wu (see, e.g., Col. 2, L. 40-60 and Col. 3, L. 30-33) discloses that the materials of substrate 200, dielectric 212 and dielectric 214 have the same compositions as the corresponding exemplary materials disclosed by the applicant for forming the substrate, the first dielectric material and the second dielectric material, respectively (see, Specification, Par. [0025], [0028], and [0031]: silicon, silicon nitride, and silicon oxide, respectively). Furthermore, one of ordinary skill in the semiconductor art would have known that a material’s thermal expansion coefficient (CTE) is a property intrinsic to said material, and that the CTE of Si is about 2.6 10-6 K-1, the CTE of SiO2 is about 0.55 10-6 K-1, and the CTE of SiN is about 3.2 10-6 K-1, as evinced by NPL “Coefficient of Thermal Expansion (CTE)”.
Accordingly, the materials of 200, 212 and 214 do have a relative arrangement of thermal expansion coefficients, wherein the silicon substrate 200 has a thermal expansion coefficient that is in between the thermal expansion coefficient of silicon nitride dielectric 212 and the thermal expansion coefficient of silicon oxide dielectric 214. Therefore, Wu in view of NPL CTE teaches that the substrate thermal expansion coefficient is in between the first thermal expansion coefficient and the second thermal expansion coefficient.
Regarding Claims 24 and 25, Wu (see, e.g., Col. 2, L. 40-60 and Col. 3, L. 30-33) discloses that the materials of substrate 200, dielectric 212 and dielectric 214 have the same compositions as the corresponding exemplary materials disclosed by the applicant for forming the substrate, the first dielectric material and the second dielectric material, respectively (see, Specification, Par. [0025], [0028], and [0031]: silicon, silicon nitride, and silicon oxide, respectively). Furthermore, one of ordinary skill in the semiconductor art would have known that a material’s thermal expansion coefficient (CTE) is a property intrinsic to said material, and that the CTE of Si is about 2.6 10-6 K-1, the CTE of SiO2 is about 0.55 10-6 K-1, and the CTE of SiN is about 3.2 10-6 K-1, as evinced by NPL “Coefficient of Thermal Expansion (CTE)”.
Accordingly, the materials of 212 and 214 do have a relative arrangement of thermal expansion coefficients, wherein the thermal expansion coefficient of silicon nitride dielectric 212 is greater than the thermal expansion coefficient of silicon oxide dielectric 214. Therefore, Wu in view of NPL CTE teaches that the first thermal expansion coefficient is greater than the second thermal expansion coefficient, as required by claim 24.
Additionally, the materials of 200, 212 and 214 do have a relative arrangement of thermal expansion coefficients, wherein the silicon substrate 200 has a thermal expansion coefficient that is in between the thermal expansion coefficient of silicon nitride dielectric 212 and the thermal expansion coefficient of silicon oxide dielectric 214. Therefore, Wu in view of NPL CTE teaches that a thermal expansion coefficient of the substrate is between the first thermal expansion coefficient and the second thermal expansion coefficient, as required by claim 25.
Claims 11, 13, 24-25, and 29 are rejected under 35 U.S.C. 103 as obvious over Lee et al. (US2020/0357703) in view of NPL “Coefficient of Thermal Expansion (CTE)” (hereinafter NPL CTE).
Regarding Claim 11, Lee (see, e.g., Par. [0031],[0044],[0047]) discloses that the materials of substrate 102, dielectric 306 and dielectric 402 have the same compositions as the corresponding exemplary materials disclosed by the applicant for forming the substrate, the first dielectric material and the second dielectric material, respectively (see, Specification, Par. [0025], [0028], and [0031]: silicon, silicon nitride, and silicon oxide, respectively). Also, see comments stated above in Par. 36-37 with regards to Claim 11, which are considered repeated here, as applied to the CTEs of substrate 102, dielectric 306 and dielectric 402. Therefore, Lee in view of NPL CTE teaches that the substrate thermal expansion coefficient is in between the first thermal expansion coefficient and the second thermal expansion coefficient.
Regarding Claim 13, Lee (see, e.g., Par. [0041],[0044],[0047]) discloses that the materials of liner 304, dielectric 306 and dielectric 402 have the same compositions as the corresponding exemplary materials disclosed by the applicant for forming the liner, the first dielectric material and the second dielectric material, respectively (see, Specification, Par. [0027], [0028], and [0031]: aluminum oxide, silicon nitride, and silicon oxide, respectively). Furthermore, one of ordinary skill in the semiconductor art would have known that a material’s thermal expansion coefficient (CTE) is a property intrinsic to said material, and that the CTE of aluminum oxide is about 6-7 10-6 K-1, the CTE of SiO2 is about 0.55 10-6 K-1, and the CTE of SiN is about 3.2 10-6 K-1, as evinced by NPL “Coefficient of Thermal Expansion (CTE)”.
Accordingly, the materials of 304, 306 and 402 do have a relative arrangement of thermal expansion coefficients, wherein the thermal expansion coefficient of the silicon nitride dielectric 306 is less than a thermal expansion coefficient of the aluminum oxide dielectric liner 304, and the thermal expansion coefficient of the silicon nitride dielectric 306 is greater than the thermal expansion coefficient of the silicon oxide dielectric 402. Therefore, Lee in view of NPL CTE teaches that the first thermal expansion coefficient of the first dielectric material is less than a thermal expansion coefficient of the dielectric liner, and the first thermal expansion coefficient of the first dielectric material is greater than the second thermal expansion coefficient of the second dielectric material.
Regarding Claims 24 and 25, Lee (see, e.g., Par. [0041],[0044],[0047]) discloses that the materials of substrate 102, dielectric 306 and dielectric 402 have the same compositions as the corresponding exemplary materials disclosed by the applicant for forming the substrate, the first dielectric material and the second dielectric material, respectively (see, Specification, Par. [0025], [0028], and [0031]: silicon, silicon nitride, and silicon oxide, respectively). Furthermore, one of ordinary skill in the semiconductor art would have known that a material’s thermal expansion coefficient (CTE) is a property intrinsic to said material, and that the CTE of Si is about 2.6 10-6 K-1, the CTE of SiO2 is about 0.55 10-6 K-1, and the CTE of SiN is about 3.2 10-6 K-1, as evinced by NPL “Coefficient of Thermal Expansion (CTE)”.
Accordingly, the materials of 306 and 402 do have a relative arrangement of thermal expansion coefficients, wherein the thermal expansion coefficient of silicon nitride dielectric 306 is greater than the thermal expansion coefficient of silicon oxide dielectric 402. Therefore, Lee in view of NPL CTE teaches that the first thermal expansion coefficient is greater than the second thermal expansion coefficient, as required by claim 24.
Additionally, the materials of 102, 306 and 402 do have a relative arrangement of thermal expansion coefficients, wherein the silicon substrate 102 has a thermal expansion coefficient that is in between the thermal expansion coefficient of silicon nitride dielectric 306 and the thermal expansion coefficient of silicon oxide dielectric 402. Therefore, Lee in view of NPL CTE teaches that a thermal expansion coefficient of the substrate is between the first thermal expansion coefficient and the second thermal expansion coefficient, as required by claim 25.
Regarding Claim 29, Lee (see, e.g., Par. [0041],[0044],[0047]) discloses that the materials of liner 304, dielectric 306 and dielectric 402 have the same compositions as the corresponding exemplary materials disclosed by the applicant for forming the liner, the first dielectric material and the second dielectric material, respectively (see, Specification, Par. [0027], [0028], and [0031]: aluminum oxide, silicon nitride, and silicon oxide, respectively). Also, see comments stated above in Par. 43-44 with regards to Claim 13, which are considered repeated here. Therefore, Lee in view of NPL CTE teaches that the first thermal expansion coefficient is less than a thermal expansion coefficient of the dielectric liner, and the second thermal expansion coefficient is less than the first thermal expansion coefficient.
Claims 11 and 24-25 are rejected under 35 U.S.C. 103 as obvious over Kuo et al. (US2019/0097056) in view of NPL “Coefficient of Thermal Expansion (CTE)” (hereinafter NPL CTE).
Regarding Claim 11, Kuo (see, e.g., Par. [0011],[0054]) discloses that the materials of substrate 100, dielectric 192 and dielectric 200 have the same compositions as the corresponding exemplary materials disclosed by the applicant for forming the substrate, the first dielectric material and the second dielectric material, respectively (see, Specification, Par. [0025], [0028], and [0031]: silicon, silicon nitride, and silicon oxide, respectively). Also, see comments stated above in Par. 36-37 with regards to Claim 11, which are considered repeated here, as applied to the CTEs of substrate 100, dielectric 192 and dielectric 200. Therefore, Kuo in view of NPL CTE teaches that the substrate thermal expansion coefficient is in between the first thermal expansion coefficient and the second thermal expansion coefficient.
Regarding Claims 24 and 25, Kuo (see, e.g., Par. [0011],[0054]) discloses that the materials of substrate 100, dielectric 192 and dielectric 200 have the same compositions as the corresponding exemplary materials disclosed by the applicant for forming the substrate, the first dielectric material and the second dielectric material, respectively (see, Specification, Par. [0025], [0028], and [0031]: silicon, silicon nitride, and silicon oxide, respectively). Furthermore, one of ordinary skill in the semiconductor art would have known that a material’s thermal expansion coefficient (CTE) is a property intrinsic to said material, and that the CTE of Si is about 2.6 10-6 K-1, the CTE of SiO2 is about 0.55 10-6 K-1, and the CTE of SiN is about 3.2 10-6 K-1, as evinced by NPL “Coefficient of Thermal Expansion (CTE)”.
Accordingly, the materials of 192 and 200 do have a relative arrangement of thermal expansion coefficients, wherein the thermal expansion coefficient of silicon nitride dielectric 192 is greater than the thermal expansion coefficient of silicon oxide dielectric 200. Therefore, Kuo in view of NPL CTE teaches that the first thermal expansion coefficient is greater than the second thermal expansion coefficient, as required by claim 24.
Additionally, the materials of 100, 192 and 200 do have a relative arrangement of thermal expansion coefficients, wherein the silicon substrate 100 has a thermal expansion coefficient that is in between the thermal expansion coefficient of silicon nitride dielectric 192 and the thermal expansion coefficient of silicon oxide dielectric 200. Therefore, Kuo in view of NPL CTE teaches that a thermal expansion coefficient of the substrate is between the first thermal expansion coefficient and the second thermal expansion coefficient, as required by claim 25.
Claims 12, 14-17, 20-22, and 27-28 are rejected under 35 U.S.C. 103 as obvious over Kuo et al. (US2019/0097056) in view of Chuang et al. (US2015/0200127).
Regarding Claim 12, Kuo (see, e.g., Fig. 15 and Par. [0053]) shows forming a liner over the substrate and the fin structures before the forming of the first dielectric material (e.g., liner 190 over top surface of 100 and over top and side surfaces of 160, 170). However, while Kuo discloses that liner 190 can be formed by any suitable material, he is silent about the liner being a dielectric liner.
Chuang (see, e.g., Fig. 1F and Par. [0016]), on the other hand and in the same field of endeavor, teaches forming a conformal liner 309 over a top surface of substrate 100 and over top and side surfaces of fins 112, so as to implement an isolation structure between fins, wherein the material of the liner can be silicon oxide or metal oxide (e.g., oxide of aluminum or titanium).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to have a step of forming a dielectric liner in the method of Kuo, because silicon oxide and aluminum oxide are known suitable materials for implementing a liner in a fin isolation structure, as suggested by Chuang, and selecting a known material based on its suitability for its intended use would have been obvious to the skilled artisan. See, Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding Claim 14, Kuo (see, e.g., Fig. 16) shows that the fin structures (e.g., 160,170) are exposed from the liner (e.g., 190). Additionally, Chuang teaches that liner 309 is a dielectric liner.
Regarding Claim 15, Kuo (see, e.g., Fig. 16) shows that the liner (e.g., 190) and the first dielectric material (e.g., 192) respectively has an U-shape. Additionally, Chuang teaches that liner 309 is a dielectric liner.
Regarding Claim 16, Kuo (see, e.g., Fig. 16) shows that a topmost surface of the liner (e.g., 190), a topmost surface of the first dielectric material (e.g., 192) and a top surface of the second dielectric material (e.g., 200) are level with each other. Additionally, Chuang teaches that liner 309 is a dielectric liner.
Regarding Claim 17, Kuo (see, e.g., Figs. 14-16) shows most aspects of the instant invention, including a method for forming a semiconductor structure, comprising:
- forming a first trench (e.g., deep isolation trench with at least depth d2) and a second trench (e.g., shallow isolation trench with depth d1) in a substrate (see, e.g., Par. [0011]: 100 of silicon material), wherein a depth of the first trench is greater than a depth of the second trench, and the first trench and the second trench are separated from each other by a fin structure (see, e.g., Fig. 14)
- forming a liner (e.g., liner 190) in the first trench and the second trench (see, e.g., Fig. 15)
- forming a first dielectric material (e.g., dielectric 192) over the liner in the first trench and the second trench, wherein the first dielectric material has a first thermal expansion coefficient (see, e.g., Par. [0054]: dielectric 192 of silicon nitride material) (see, e.g., Fig. 16)
- forming a second dielectric material (e.g., dielectric 200) over the first dielectric material in the first trench and the second trench, wherein the second dielectric material has a second thermal expansion coefficient (see, e.g., Par. [0054]: 200 of silicon oxide material) (see, e.g., Fig. 16)
- recessing the second dielectric material to form a first isolation structure in the first trench and a second isolation structure in the second trench (see, e.g., Par. [0054]: 200 is partially removed, by CMP and recessing, to form STI structures between fins) (see, e.g., Fig. 16)
However, while Kuo discloses that liner 190 can be formed by any suitable material, he is silent about the liner being a dielectric liner. Also, see comments stated above in Par. 56-57 with regards to Claim 12, which are considered repeated here.
Regarding Claim 20, Kuo (see, e.g., Fig. 16) shows recessing the first dielectric material along with the recessing of the second dielectric material (see, e.g., Par. [0054]: 192 and 200 are partially removed together, by CMP and recessing, to form STI structures between fins).
Regarding Claim 21, Kuo (see, e.g., Fig. 16) shows that a width of the first trench (e.g., deep isolation trench between fins 160 and 170) is greater than a width of the second trench (e.g., shallow isolation trench between fins 160).
Regarding Claim 22, Kuo (see, e.g., Fig. 15) shows that a bottommost surface of the liner (e.g., 190) in the first trench (e.g., deep isolation trench) and a bottommost surface of the liner in the second trench (e.g., shallow isolation trench) are at different levels. Additionally, Chuang teaches that liner 309 is a dielectric liner.
Regarding Claim 27, Kuo (see, e.g., Fig. 15 and Par. [0053]) shows forming a liner over the substrate, the trench and the fin structure prior the forming of the first dielectric material (e.g., liner 190 over top surface of 100 and over top and side surfaces of 160, 170). However, while Kuo discloses that liner 190 can be formed by any suitable material, he is silent about the liner being a dielectric liner. Also, see comments stated above in Par. 56-57 with regards to Claim 12, which are considered repeated here.
Regarding Claim 28, Kuo (see, e.g., Fig. 16) shows that the fin structure (e.g., 160,170) is exposed from the liner (e.g., 190). Additionally, Chuang teaches that liner 309 is a dielectric liner.
Claim 18 is rejected under 35 U.S.C. 103 as obvious over Kuo et al. (US2019/0097056) in view of Chuang et al. (US2015/0200127), and in further view of NPL “Coefficient of Thermal Expansion (CTE)” (hereinafter NPL CTE).
Regarding Claim 18, Kuo (see, e.g., Par. [0011],[0054]) discloses that the materials of substrate 100, dielectric 192 and dielectric 200 have the same compositions as the corresponding exemplary materials disclosed by the applicant for forming the substrate, the first dielectric material and the second dielectric material, respectively (see, Specification, Par. [0025], [0028], and [0031]: silicon, silicon nitride, and silicon oxide, respectively). Also, see comments stated above in Par. 36-37 with regards to Claim 11, which are considered repeated here, as applied to the CTEs of substrate 100, dielectric 192 and dielectric 200. Therefore, Kuo in view of Chuang and in further view of NPL CTE teaches that the substrate thermal expansion coefficient is in between the first thermal expansion coefficient and the second thermal expansion coefficient.
Conclusion
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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